Regulator circuit and semiconductor memory device including the same

Abstract

A semiconductor memory device includes a charge pump circuit for generating a pass pump voltage in response to a clock signal and a pump enable signal and a regulator circuit for maintaining the pass pump voltage in the same level as a program pass voltage during a program operation and discharging the program pass voltage during a verification operation so that the program pass voltage has the same level as a verification pass voltage.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a charge pump circuit configured to generate a pass pump voltage in response to a clock signal and a pump enable signal; and 
 a regulator circuit configured to regulate the pass pump voltage to output a program pass voltage during a program operation and discharge the program pass voltage to output a verification pass voltage during a verification operation; 
 wherein the regulator circuit detects the program pass voltage in a period during which the program operation switches to the verification operation and controls a period in which the program pass voltage is discharged, and 
 wherein the regulator circuit comprises: 
 a regulator configured to receive the pass pump voltage and a bandgap voltage and generate the program pass voltage; 
 a discharge circuit configured to discharge the program pass voltage to a predetermined voltage level by comparing the bandgap voltage and a feedback voltage, generated by the regulator; and 
 a control circuit configured to generate a control signal for enabling the discharge circuit in response to a regulator discharge control signal, generated by the discharge circuit and a regulator discharge signal activated for a predetermined time during the period in which the program operation switches to the verification operation. 
 
     
     
       2. The semiconductor memory device of  claim 1 , further comprising a switching circuit configured to supply the program pass voltage or the verification pass voltage to a word line. 
     
     
       3. The semiconductor memory device of  claim 2 , further comprising a word line discharge circuit configured to discharge the word line in response to a discharge signal. 
     
     
       4. The semiconductor memory device of  claim 1 , wherein the regulator comprises:
 a pass voltage generator configured to generate the program pass voltage by down-converting the pass pump voltage in response to a comparison signal; 
 a feedback voltage generator configured to generate the feedback voltage by distributing the program pass voltage in a predetermined distribution ratio; and 
 a comparison signal generator configured to generate the comparison signal by comparing the feedback voltage and the bandgap voltage. 
 
     
     
       5. The semiconductor memory device of  claim 1 , wherein the discharge circuit comprises:
 a differential amplifier unit configured to generate the regulator discharge control signal by comparing the bandgap voltage and the feedback voltage; and 
 a discharge unit configured to discharge the program pass voltage in response to the regulator discharge control signal. 
 
     
     
       6. The semiconductor memory device of  claim 1 , wherein, even when the regulator discharge signal becomes inactivated after being activated for the predetermined time during a period in which the program operation switches to the verification operation, the control circuit activates and outputs the control signal if the program pass voltage is higher than the verification pass voltage. 
     
     
       7. A regulator circuit, comprising:
 a regulator configured to receive a pass pump voltage and a bandgap voltage and generating a pass voltage; 
 a discharge circuit configured to discharge the pass voltage to a predetermined voltage level by comparing the bandgap voltage and a feedback voltage obtained by using the pass voltage; and 
 a control circuit configured to generate a control signal for enabling the discharge circuit in response to a regulator discharge control signal generated by the discharge circuit and a regulator discharge signal activated for a predetermined time during a period in which a program operation switches to a verification operation. 
 
     
     
       8. The regulator circuit of  claim 7 , wherein the regulator comprises:
 a pass voltage generator configured to generate the pass voltage by down-converting the pass pump voltage in response to a comparison signal; 
 a feedback voltage generator configured to generate the feedback voltage by distributing the pass voltage in a predetermined distribution ratio; and 
 a comparison signal generator configured to generate the comparison signal by comparing the feedback voltage and the bandgap voltage. 
 
     
     
       9. The regulator circuit of  claim 7 , wherein the discharge circuit comprises:
 a differential amplifier unit configured to generate the regulator discharge control signal by comparing the bandgap voltage and the feedback voltage; and 
 a discharge unit configured to discharge the pass voltage in response to the regulator discharge control signal. 
 
     
     
       10. The regulator circuit of  claim 7 , wherein, even when the regulator discharge signal becomes inactivated after being activated for the predetermined time during the period in which the program operation switches to the verification operation, the control circuit activates and outputs the control signal if the pass voltage is higher than a target voltage. 
     
     
       11. The regulator circuit of  claim 7 , wherein the discharge circuit compares the feedback voltage and the bandgap voltage and discharges the pass voltage when the feedback voltage is higher than the bandgap voltage. 
     
     
       12. A semiconductor memory device, comprising:
 a charge pump circuit configured to generate a pass pump voltage in response to a clock signal and a pump enable signal; 
 a regulator circuit configured to receive the pass pump voltage and generating a program pass voltage; and 
 a switching circuit configured to supply the program pass voltage to a word line, 
 wherein the regulator circuit detects the program pass voltage in a period during which a program operation switches to a verification operation and controls a period in which the program pass voltage is discharged to provide a verification pass voltage used in the verification operation, and 
 wherein the regulator circuit comprises: 
 a regulator configured to receive the pass pump voltage and a bandgap voltage and generate the program pass voltage; 
 a discharge circuit configured to discharge the program pass voltage to a predetermined voltage level by comparing the bandgap voltage and a feedback voltage, generated by the regulator; and 
 a control circuit configured to generate a control signal for enabling the discharge circuit in response to a regulator discharge control signal, generated by the discharge circuit and a regulator discharge signal activated for a predetermined time during the period in which the program operation switches to the verification operation. 
 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the regulator comprises:
 a pass voltage generator configured to generate the program pass voltage by down-converting the pass pump voltage in response to a comparison signal; 
 a feedback voltage generator configured to generate the feedback voltage by distributing the program pass voltage in a predetermined distribution ratio; and 
 a comparison signal generator configured to generate the comparison signal by comparing the feedback voltage and the bandgap voltage. 
 
     
     
       14. The semiconductor memory device of  claim 12 , wherein the discharge circuit comprises:
 a differential amplifier unit configured to generate the regulator discharge control signal by comparing the bandgap voltage and the feedback voltage; and 
 a discharge unit configured to discharge the program pass voltage in response to the regulator discharge control signal. 
 
     
     
       15. The semiconductor memory device of  claim 12 , wherein, even when the regulator discharge signal becomes inactivated after being activated for the predetermined time during a period in which the program operation switches to the verification operation, the control circuit activates and outputs the control signal if the program pass voltage is higher than the verification pass voltage. 
     
     
       16. The semiconductor memory device of  claim 12 , wherein the discharge circuit compares the feedback voltage and the bandgap voltage and discharges the pass voltage when the feedback voltage is higher than the bandgap voltage.