Pipelined analog digital convertor

Abstract

A pipelined analog-to-digital converter includes a digital correction circuit configured to improve the complexity of a logic circuit for dividing a correction period and a no-correction period of a digital output. The pipelined analog-to-digital converter performs a logic correction operation via binary shifting at data error correction. Accordingly, although the resolution increases, it is possible to reduce the complexity and area of a logic circuit.

What is claimed is: 
     
       1. A pipelined analog-to-digital converter comprising:
 a conversion stage part including a plurality of serially connected conversion stages, each of the plurality of serially connected conversion stages converting an input voltage a B-bit digital code in response to at least one clock signal and outputting a residual voltage; and 
 a digital correction circuit configured to perform a logic correction operation by binary shifting the B-bit digital codes output from the plurality of serially connected conversion stages, 
 wherein each of the plurality of serially connected conversion stages comprises:
 a multiplying digital-to-analog converter configured to convert a (2 B −1)-bit digital code into an analog signal in response to the at least one clock signal and to output the residual voltage by subtracting the converted analog signal from the input voltage; and 
 an analog-to-digital sub-converter configured to convert the input voltage into the (2 B −1)-bit digital code and the B-bit digital code, 
 
 wherein the multiplying digital-to-analog converter comprises:
 a first sampler configured to sample the input voltage in response to a first clock signal; 
 a digital-to-analog converter configured to convert the (2 B −1)-bit digital code into the analog signal in response to a second clock signal; 
 a subtracter configured to subtract an output value of the digital-to-analog converter from an output of the first sampler; and 
 a residual voltage amplifier configured to output the residual voltage by amplifying an output value of the subtracter in response to the second clock signal. 
 
 
     
     
       2. The pipelined analog-to-digital converter of  claim 1 , further comprising:
 a clock signal generator configured to generate the at least one clock signal. 
 
     
     
       3. The pipelined analog-to-digital converter of  claim 1 , further comprising:
 a reference voltage buffer configured to generate a reference voltage. 
 
     
     
       4. The pipelined analog-to-digital converter of  claim 1 , wherein the first and second clock signals are complementary. 
     
     
       5. The pipelined analog-to-digital converter of  claim 4 , wherein the multiplying digital-to-analog converter performs a sampling operation in response to the first clock signal and a residual voltage amplifying operation in response to the second clock signal, and
 wherein if one of continuous conversion stages in the conversion stage part performs a sampling operation, the other performs a residual voltage amplifying operation. 
 
     
     
       6. The pipelined analog-to-digital converter of  claim 1 , wherein the analog-to-digital sub-converter comprises:
 a second sampler configured to sample the input voltage in response to the first clock signal; 
 a preprocessing amplifier string configured to amplify an output value of the second sampler; 
 a latch string configured to latch an output value of the preprocessing amplifier string in response to the second clock signal and to output the (2 B −1)-bit digital code; and 
 a decoder configured to decode an output value of the latch string into the B-bit digital code. 
 
     
     
       7. The pipelined analog-to-digital converter of  claim 1 , wherein the digital correction circuit comprises:
 a plurality of delay cells configured to delay the B-bit digital codes output from the plurality of serially connected conversion stages; and 
 a subtracter/adder block configured to perform the logic correction operation by binary shifting the delayed digital codes corresponding to the plurality of serially connected conversion stages, respectively. 
 
     
     
       8. The pipelined analog-to-digital converter of  claim 7 , wherein the subtracter/adder block receives the delayed digital codes each corresponding to the plurality of serially connected conversion stages in response to a first clock signal. 
     
     
       9. The pipelined analog-to-digital converter of  claim 7 , wherein in continuous i th  and (i+1) th  conversion stages of the plurality of serially connected conversion stages, the logic correction operation is performed such that one bit of a first digital code output from the i th  conversion stage is overlapped with one bit of a second digital code output from the (i+1) th  conversion stage. 
     
     
       10. The pipelined analog-to-digital converter of  claim 9 , wherein when the second digital code output from the (i+1) th  conversion stage is ‘000’ or ‘001’, ‘1’ is subtracted from the first digital code at the logic correction operation. 
     
     
       11. The pipelined analog-to-digital converter of  claim 9 , wherein when the second digital code output from the (i+1) th  conversion stage is ‘111’ or ‘110’, ‘1’ is added to the first digital code at the logic correction operation. 
     
     
       12. The pipelined analog-to-digital converter of  claim 9 , wherein when the second digital code output from the (i+1) th  conversion stage is ‘101’, ‘100’, ‘011’, or ‘010’, the first digital code is not corrected at the logic correction operation. 
     
     
       13. A pipelined analog-to-digital converter comprising:
 a conversion stage part including a plurality of serially connected conversion stages, each of the plurality of serially connected conversion stages converting an input voltage a B-bit digital code in response to at least one clock signal and outputting a residual voltage; and 
 a digital correction circuit configured to perform a logic correction operation by binary shifting the B-bit digital codes output from the plurality of serially connected conversion stages, 
 wherein the digital correction circuit comprises:
 a plurality of delay cells configured to delay the B-bit digital codes output from the plurality of serially connected conversion stages; and 
 a subtracter/adder block configured to perform the logic correction operation by binary shifting the delayed digital codes corresponding to the plurality of serially connected conversion stages, respectively, 
 
 wherein in continuous i th  and (i+1) th  conversion stages of the plurality of serially connected conversion stages, the logic correction operation is performed such that one bit of a first digital code outputted from the i th  conversion stage is overlapped with one bit of a second digital code outputted from the (i+1) th  conversion stage, 
 wherein the subtracter/adder block is configured to output the first digital code of the i th  conversion stage as upper bits of a corrected digital code and remaining bits other than a most significant bit of the second digital code of the (i+1) th  conversion stage as lower bits of the corrected digital code in response to a first signal, and comprises:
 a subtracter configured to output a value, obtained by subtracting a first predetermined value from the first digital code of the i th  conversion stage, as the upper bits of the corrected digital code in response to a second signal; 
 a first adder configured to output a value, obtained by adding the first predetermined value to the first digital code of the i th  conversion stage, as the upper bits of the corrected digital code in response to a third signal; 
 a second adder configured to output a shift code by adding a second predetermined value to the second digital code; and 
 a decoder configured to generate the first, second, and third signals in response to the shift code. 
 
 
     
     
       14. The pipelined analog-to-digital converter of  claim 13 , wherein the first signal is a first bit value of the shift code. 
     
     
       15. The pipelined analog-to-digital converter of  claim 13 , wherein the second signal is a value obtained by multiplying an inverted version of the first bit value of the shift code and a second bit value of the shift code. 
     
     
       16. The pipelined analog-to-digital converter of  claim 13 , wherein the third signal is a value obtained by multiplying an inverted version of the first bit value of the shift code and an inverted version of the second bit value of the shift code. 
     
     
       17. The pipelined analog-to-digital converter of  claim 13 , wherein the first predetermined value is ‘001’. 
     
     
       18. The pipelined analog-to-digital converter of  claim 13 , wherein the second predetermined value is ‘010’.