Templated circuitry fabrication

Abstract

A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

What is claimed is: 
     
       1. A method of making templated circuitry, the method comprising:
 providing a template on a conductive surface of a carrier, the template being an insulator and comprising multiple levels and multiple regions associated with the multiple levels, a first level of the template exposing the conductive surface; 
 electrochemically depositing a first metal on the conductive surface in first regions of the first level; 
 depositing a circuit material to cover the first metal; 
 etching the template until a second level of the template exposes the conductive surface in second regions on opposite sides of and spaced from the first regions; 
 electrochemically depositing a second metal on the conductive surface in the second regions; and 
 transferring the template of deposited materials from the carrier to a substrate. 
 
     
     
       2. The method of making templated circuitry of  claim 1 , further comprising patterning the template, wherein patterning the template comprises:
 incorporating regions of substantially uniform size on the multiple levels; 
 limiting a maximum size of the multiple regions using segmentation of large regions into an interconnected array of relatively smaller regions; 
 incorporating non-operational regions on respective levels to produce a substantially uniform region density per level; 
 incorporating different region densities on different levels; and 
 incorporating redundant regions on the multiple levels. 
 
     
     
       3. The method of making templated circuitry of  claim 2 , wherein the template is formed in a polymeric resist material using one or more of photolithography, embossing, nanoimprint lithography and laser patterning. 
     
     
       4. The method of making templated circuitry of  claim 1 , wherein the circuit material is deposited using one or more of electrochemical deposition, slot coating, spray deposition and inkjet printing. 
     
     
       5. The method of making templated circuitry of  claim 1 , wherein the second level of the template is etched using plasma etching. 
     
     
       6. The method of making templated circuitry of  claim 1 , wherein transferring the template of deposited materials comprises:
 attaching the substrate to an exposed surface of the template with an adhesive; and 
 removing the carrier to expose an opposite surface of the template. 
 
     
     
       7. The method of making templated circuitry of  claim 1 , wherein the substrate is one or both of flexible and transparent. 
     
     
       8. The method of making templated circuitry of  claim 1 , wherein the electrochemically deposited second metal forms an electrically conductive bridge across the circuit material from the opposite sides of the first region. 
     
     
       9. The method of making templated circuitry of  claim 8 , wherein the circuit material is one of an insulator material, a resistive material, and a high dielectric constant dielectric material, the circuitry comprising a respective one of a crossover, a resistor, and a capacitor. 
     
     
       10. The method of making templated circuitry of  claim 8 , wherein the circuit material is a semiconductor material, the circuitry comprising a diode, and wherein depositing the circuit material comprises doping the semiconductor material to create a horizontally stacked semiconductor junction. 
     
     
       11. The method of making templated circuitry of  claim 1 , wherein the electrochemically deposited second metal from the second regions on the opposite sides of the first region leaves a gap over the circuit material. 
     
     
       12. The method of making templated circuitry of  claim 11 , wherein the circuit material is an insulator material, the method further comprising depositing a device material to fill the gap. 
     
     
       13. The method of making templated circuitry of  claim 11 , wherein the device material is a resistive material, the circuitry comprising a resistor and first region conductor traces at the first level insulated from the resistor. 
     
     
       14. The method of making templated circuitry of  claim 11 , wherein the device material is a semiconductor material, the circuitry comprising field effect transistors (FETs), the first metal in the first regions being respective gates of the FETs. 
     
     
       15. The method of making templated circuitry of  claim 11 , wherein the device material is a semiconductor material, and wherein depositing the device material comprises doping the semiconductor material to create a vertically stacked semiconductor junction, the circuitry comprising a diode and first region conductor traces at the first level insulated from the diode. 
     
     
       16. The method of making templated circuitry of  claim 11 , wherein the device material is a semiconductor material, the method further comprising selectively removing the insulator material exposed in the gap before the device material is deposited, and wherein depositing the device material comprises doping the semiconductor material to form a vertically stacked semiconductor junction, the circuitry comprising bipolar junction transistors (BJTs), the first metal in the first regions being respective bases of the BJTs.