Multiphase local oscillator generator circuit for a broadband tuner device

Abstract

Embodiments of integrated circuits for use in a broadband tuner are described. In one embodiment, an integrated circuit includes a clock buffer configured to buffer a received clock signal and generate a buffered clock signal. Additionally, the integrated circuit includes a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted. The integrated circuit may also include a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals.

What is claimed is: 
     
       1. An integrated circuit comprising:
 a clock buffer configured to buffer a received clock signal and generate a buffered clock signal; 
 a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted; and 
 a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals, 
 wherein at least one of:
 the clock buffer is configured to reduce spurious and harmonic anomalies in the received clock signal; 
 the clock buffer is configured to generate a clock signal output having a stable common-mode voltage; 
 the clock buffer comprises a feedback control mechanism for regulating a common-mode voltage level of the clock buffer output with a reference voltage source; or 
 the clock buffer comprises:
 a driver stage having a plurality of AC-coupled differential transistor pairs; and 
 an output stage AC-coupled to the driver stage, wherein the output stage is configured to generate the buffered clock signal without introducing DC offsets. 
 
 
 
     
     
       2. An integrated circuit comprising:
 a clock buffer configured to buffer a received clock signal and generate a buffered clock signal; 
 a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted; and 
 a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals, 
 wherein the multiphase local oscillator core comprises a plurality of flip-flop devices arranged in a ring configuration. 
 
     
     
       3. The integrated circuit of  claim 2 , further comprising a plurality of isolation resistors, each isolation resistor being coupled between one of the plurality of flip-flop devices and one of the plurality of output buffers. 
     
     
       4. The integrated circuit of  claim 3 , wherein each of the plurality of isolation resistors is physically positioned closer in proximity to one of the plurality of flip-flops than to one of the plurality of output buffers along a signal conducting line between the one of the plurality of flip-flops and the one of the plurality of output buffers. 
     
     
       5. The integrated circuit of  claim 4 , wherein each of the plurality of isolation resistors is positioned adjacent to an output port of one of the flip-flops. 
     
     
       6. The integrated circuit of  claim 4 , wherein each of the plurality of isolation resistors is configured to isolate one of the plurality of flip-flops from parasitic capacitance on the signal-conducting line between each of the plurality of flip-flops and a corresponding one of the plurality of output buffers. 
     
     
       7. An integrated circuit comprising:
 a clock buffer configured to buffer a received clock signal and generate a buffered clock signal; 
 a multiphase local oscillator core coupled to the clock buffer and configured to generate a plurality of oscillator signals in response to the buffered clock signal, each of the plurality of oscillator signals being mutually phase shifted; and 
 a plurality of output buffers, each configured to receive one of the plurality of oscillator signals and to produce an output signal suitable for use in a broadband tuner circuit in response to the one of the plurality of oscillator signals, 
 wherein at least one of:
 each of the plurality of output buffers comprises an open-loop circuit; 
 each of the plurality of output buffers comprises a plurality of diode-connected transistors arranged to provide control of supply voltages used to generate the output signal; or 
 each of the plurality of output buffers comprises a plurality of inverters arranged to buffer a differential clock signal. 
 
 
     
     
       8. The integrated circuit of  claim 7 , wherein each of the plurality of output buffers comprises a plurality of power supply rails, each power supply rail configured to supply a prescribed voltage to at least one pair of inverters arranged to buffer a differential clock signal. 
     
     
       9. A broadband tuner chip comprising:
 a harmonic rejection mixer having a multiphase local oscillator generator configured to generate a plurality of phase shifted clock signals in response to a single input clock signal received from a clock source, wherein the multiphase local oscillator generator is configured to operate at high frequencies and avoid phase errors through use of an input clock buffer coupled to a multiphase local oscillator core, the multiphase local oscillator core being coupled to an output buffer, 
 wherein the multiphase local oscillator core comprises a plurality of flip-flop devices arranged in a ring configuration, the output of each of the flip-flop devices being coupled to an input of an output buffer. 
 
     
     
       10. A broadband tuner chip comprising:
 a harmonic rejection mixer having a multiphase local oscillator generator configured to generate a plurality of phase shifted clock signals in response to a single input clock signal received from a clock source, wherein the multiphase local oscillator generator is configured to operate at high frequencies and avoid phase errors through use of an input clock buffer coupled to a multiphase local oscillator core, the multiphase local oscillator core being coupled to an output buffer; and 
 a plurality of isolation resistors, each isolation resistor being coupled between one of the plurality of flip-flop devices and one of the plurality of output buffers. 
 
     
     
       11. The broadband tuner of  claim 10 , wherein each of the plurality of isolation resistors is physically positioned closer in proximity to one of the plurality of flip-flops than to one of the plurality of output buffers along a signal conducting line between the one of the plurality of flip-flops and the one of the plurality of output buffers. 
     
     
       12. A broadband tuner chip comprising:
 a harmonic rejection mixer having a multiphase local oscillator generator configured to generate a plurality of phase shifted clock signals in response to a single input clock signal received from a clock source, wherein the multiphase local oscillator generator is configured to operate at high frequencies and avoid phase errors through use of an input clock buffer coupled to a multiphase local oscillator core, the multiphase local oscillator core being coupled to an output buffer, 
 wherein the output buffer comprises a plurality of inverter circuits arranged in an open-loop configuration, and having a plurality of diode-connected transistors coupled to a voltage supply rail for controlling a voltage level supplied to the plurality of inverters.