Electronic circuit, semiconductor device, and electronic device

Abstract

The electronic circuit includes a first comparator and a second comparator in which an induced electromotive force of a coil are compared with each of a first reference potential and a second reference potential and which output a pulse signal in accordance with conditions; the first signal processing circuit which outputs a first receiving rectangular wave signal and a first error signal in accordance with conditions of the pulse signal output from the first comparator and in which data held in accordance with conditions of pulse signal output from the second comparator is reset; and the second signal processing circuit which outputs a second receiving rectangular wave signal and a second error signal in accordance with conditions of the pulse signal output from the second comparator and in which data held in accordance with conditions of pulse signal output from the first comparator is reset.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a coil configured to generate an induced electromotive force by utilizing electromagnetic induction; 
 a first comparator configured to compare the induced electromotive force with a first reference potential and to output a first pulse signal in the case where the induced electromotive force is higher than the first reference potential; 
 a second comparator configured to compare the induced electromotive force with a second reference potential and output a second pulse signal in the case where the induced electromotive force is lower than the second reference potential; 
 a first signal processing circuit, 
 wherein the first signal processing circuit is configured to output a first receiving rectangular wave signal when the first pulse signal is output, 
 wherein the first signal processing circuit is configured to output a first error signal when the first pulse signal is output twice or more in succession, and 
 wherein a data in the first signal processing circuit is reset when the second pulse signal is output; and 
 a second signal processing circuit, 
 wherein the second signal processing circuit is configured to output a second receiving rectangular wave signal when the second pulse signal is output, 
 wherein the second signal processing circuit is configured to output a second error signal when the second pulse signal is output twice or more in succession, and 
 wherein a data in the second signal processing circuit is reset when the first pulse signal is output. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein the first signal processing circuit comprises a first D-type flip-flop and a second D-type flip-flop, 
 wherein the first D-type flip-flop comprises a first clock terminal, a first output terminal, a first inverted output terminal, a first data input terminal, and a first reset terminal, 
 wherein the second D-type flip-flop comprises a second clock terminal, a second output terminal, a second inverted output terminal, a second data input terminal, and a second reset terminal, 
 wherein the second signal processing circuit comprises a third D-type flip-flop and a fourth D-type flip-flop, 
 wherein the third D-type flip-flop comprises a third clock terminal, a third output terminal, a third inverted output terminal, a third data input terminal, and a third reset terminal, 
 wherein the fourth D-type flip-flop comprises a fourth clock terminal, a fourth output terminal, a fourth inverted output terminal, a fourth data input terminal, and a fourth reset terminal, 
 wherein the first pulse signal is input to the first clock terminal, the third reset terminal, and the fourth reset terminal, 
 wherein the first receiving rectangular wave signal is output from the first output terminal, 
 wherein an inverted output signal of the first receiving rectangular wave signal is input to the first data input terminal and the second clock terminal, 
 wherein the first error signal is output from the second output terminal, 
 wherein an inverted output signal of the first error signal is input to the second data input terminal, 
 wherein the second pulse signal is input to the third clock terminal, the first reset terminal, and the second reset terminal, 
 wherein the second receiving rectangular wave signal is output from the third output terminal, 
 wherein an inverted output signal of the second receiving rectangular wave signal is input to the third data input terminal and the fourth clock terminal, 
 wherein the second error signal is output from the fourth output terminal, and 
 wherein an inverted output signal of the second error signal is input to the fourth data input terminal. 
 
     
     
       3. The semiconductor device according to  claim 1 , further comprising:
 a first inverter circuit between the second comparator and the first signal processing circuit; and 
 a second inverter circuit between the first comparator and the second signal processing circuit, 
 wherein the first signal processing circuit comprises a first T-type flip-flop and a second T-type flip-flop, 
 wherein the first T-type flip-flop comprising a first count input terminal, a first output terminal, a first inverted output terminal, and a first inversion reset terminal, 
 wherein the second T-type flip-flop comprises a second count input terminal, a second output terminal, a second inverted output terminal, and a second inversion reset terminal, 
 wherein the first pulse signal is input to the first count input terminal and the second inverter circuit, 
 wherein the first receiving rectangular wave signal is output from the first output terminal and is input to the second count input terminal, 
 wherein the second signal processing circuit comprises a third T-type flip-flop and a fourth T-type flip-flop, 
 wherein the third T-type flip-flop comprises a third count input terminal, a third output terminal, a third inverted output terminal, and a third inversion reset terminal, 
 wherein the fourth T-type flip-flop comprises a fourth count input terminal, a fourth output terminal, a fourth inverted output terminal, and a fourth inversion reset terminal, 
 wherein the second pulse signal is input to the third count input terminal and the first inverter circuit, and 
 wherein the second receiving rectangular wave signal is output from the third output terminal and is input to the fourth count input terminal. 
 
     
     
       4. A semiconductor device comprising:
 a first integrated circuit comprising a transmitting circuit; and 
 a second integrated circuit comprising a receiving circuit, 
 wherein the transmitting circuit comprises a first coil configured to output a transmitting signal, 
 wherein the receiving circuit comprises:
 a second coil configured to generate an induced electromotive force by utilizing electromagnetic induction in accordance to the transmitting signal; 
 a first comparator configured to compare the induced electromotive force with a first reference potential and to output a first pulse signal in the case where the induced electromotive force is higher than the first reference potential; 
 a second comparator configured to compare the induced electromotive force with a second reference potential and outputs a second pulse signal in the case where the induced electromotive force is lower than the second reference potential; 
 a first signal processing circuit, 
 wherein the first signal processing circuit is configured to output a first receiving rectangular wave signal when the first pulse signal is output, 
 wherein the first signal processing circuit is configured to output a first error signal when the first pulse signal is output twice or more in succession; and 
 wherein a data is reset when the second pulse signal is output is reset; and 
 a second signal processing circuit, 
 wherein the second signal processing circuit is configured to output a second receiving rectangular wave signal when the second pulse signal is output, 
 wherein the second signal processing circuit is configured to output a second error signal when the second pulse signal is output twice or more in succession, and 
 wherein a data in the second signal processing circuit is reset when the first pulse signal is output. 
 
 
     
     
       5. The semiconductor device according to  claim 4 ,
 wherein the first signal processing circuit comprises a first D-type flip-flop and a second D-type flip-flop, 
 wherein the first D-type flip-flop comprises a first clock terminal, a first output terminal, a first inverted output terminal, a first data input terminal, and a first reset terminal, 
 wherein the second D-type flip-flop comprises a second clock terminal, a second output terminal, a second inverted output terminal, a second data input terminal, and a second reset terminal, 
 wherein the second signal processing circuit comprises a third D-type flip-flop and a fourth D-type flip-flop, 
 wherein the third D-type flip-flop comprises a third clock terminal, a third output terminal, a third inverted output terminal, a third data input terminal, and a third reset terminal, 
 wherein the fourth D-type flip-flop comprises a fourth clock terminal, a fourth output terminal, a fourth inverted output terminal, a fourth data input terminal, and a fourth reset terminal, 
 wherein the first pulse signal is input to the first clock terminal, the third reset terminal, and the fourth reset terminal, 
 wherein the first receiving rectangular wave signal is output from the first output terminal, 
 wherein an inverted output signal of the first receiving rectangular wave signal is input to the first data input terminal and the second clock terminal, 
 wherein the first error signal is output from the second output terminal, 
 wherein an inverted output signal of the first error signal is input to the second data input terminal, 
 wherein the second pulse signal is input to the third clock terminal, the first reset terminal, and the second reset terminal, 
 wherein the second receiving rectangular wave signal is output from the third output terminal, 
 wherein an inverted output signal of the second receiving rectangular wave signal is input to the third data input terminal and the fourth clock terminal, 
 wherein the second error signal is output from the fourth output terminal, and 
 wherein an inverted output signal of the second error signal is input to the fourth data input terminal. 
 
     
     
       6. The semiconductor device according to  claim 5 ,
 wherein the first integrated circuit and the second integrated circuit are stacked. 
 
     
     
       7. The semiconductor device according to  claim 5 ,
 wherein the first integrated circuit and the second integrated circuit are adjacent to each other. 
 
     
     
       8. The semiconductor device according to  claim 5 ,
 wherein the first integrated circuit further comprises a receiving circuit, and 
 wherein the second integrated circuit further comprises a transmitting circuit. 
 
     
     
       9. The semiconductor device according to  claim 4 , further comprising:
 a first inverter circuit between the second comparator and the first signal processing circuit; and 
 a second inverter circuit between the first comparator and the second signal processing circuit, 
 wherein the first signal processing circuit comprises a first T-type flip-flop and a second T-type flip-flop, 
 wherein the first T-type flip-flop comprising a first count input terminal, a first output terminal, a first inverted output terminal, and a first inversion reset terminal, 
 wherein the second T-type flip-flop comprises a second count input terminal, a second output terminal, a second inverted output terminal, and a second inversion reset terminal, 
 wherein the first pulse signal is input to the first count input terminal and the second inverter circuit, 
 wherein the first receiving rectangular wave signal is output from the first output terminal and is input to the second count input terminal, 
 wherein the second signal processing circuit comprises a third T-type flip-flop and a fourth T-type flip-flop, 
 wherein the third T-type flip-flop comprises a third count input terminal, a third output terminal, a third inverted output terminal, and a third inversion reset terminal, 
 wherein the fourth T-type flip-flop comprises a fourth count input terminal, a fourth output terminal, a fourth inverted output terminal, and a fourth inversion reset terminal, 
 wherein the second pulse signal is input to the third count input terminal and the first inverter circuit, and 
 wherein the second receiving rectangular wave signal is output from the third output terminal and is input to the fourth count input terminal. 
 
     
     
       10. The semiconductor device according to  claim 9 ,
 wherein the first integrated circuit and the second integrated circuit are stacked. 
 
     
     
       11. The semiconductor device according to  claim 9 ,
 wherein the first integrated circuit and the second integrated circuit are adjacent to each other. 
 
     
     
       12. The semiconductor device according to  claim 9 ,
 wherein the first integrated circuit further comprises a receiving circuit, and 
 wherein the second integrated circuit further comprises a transmitting circuit. 
 
     
     
       13. The semiconductor device according to  claim 4 ,
 wherein the first integrated circuit and the second integrated circuit are stacked. 
 
     
     
       14. The semiconductor device according to  claim 4 ,
 wherein the first integrated circuit and the second integrated circuit are adjacent to each other. 
 
     
     
       15. The semiconductor device according to  claim 4 ,
 wherein the first integrated circuit further comprises a receiving circuit, and 
 wherein the second integrated circuit further comprises a transmitting circuit. 
 
     
     
       16. An electronic device comprising the semiconductor device according to  claim 4 . 
     
     
       17. A semiconductor device comprising:
 a coil configured to generate an induced electromotive force by utilizing electromagnetic induction; 
 a first comparator connected to the coil; 
 a second comparator connected to the coil; 
 a first signal processing circuit comprising a first D-type flip-flop and a second D-type flip-flop connected to the first D-type flip-flop; and 
 a second signal processing circuit comprising a third D-type flip-flop and a fourth D-type flip-flop connected to the third D-type flip-flop, 
 wherein the first D-type flip-flop is further connected to the first comparator and the second comparator, 
 wherein the second D-type flip-flop is further connected to the second comparator, 
 wherein the third D-type flip-flop is further connected to the first comparator and the first comparator, and 
 wherein the fourth D-type flip-flop is further connected to the first comparator. 
 
     
     
       18. The semiconductor device according to  claim 17 ,
 wherein the first comparator comprising a first non-inversion input terminal and a first inversion input terminal, 
 wherein the second comparator comprising a second non-inversion input terminal and a second inversion input terminal, 
 wherein the first D-type flip-flop comprises a first clock terminal, a first output terminal, a first inverted output terminal, a first data input terminal, and a first reset terminal, 
 wherein the second D-type flip-flop comprises a second clock terminal, a second output terminal, a second inverted output terminal, a second data input terminal, and a second reset terminal, 
 wherein the third D-type flip-flop comprises a third clock terminal, a third output terminal, a third inverted output terminal, a third data input terminal, and a third reset terminal, 
 wherein the fourth D-type flip-flop comprises a fourth clock terminal, a fourth output terminal, a fourth inverted output terminal, a fourth data input terminal, and a fourth reset terminal, 
 wherein the coil is connected to the first non-inversion input terminal and the second inversion input terminal, 
 wherein the first comparator is connected to the first clock terminal, the third reset terminal, and the fourth reset terminal, 
 wherein the second comparator is connected to the third clock terminal, the first reset terminal, and the second reset terminal, 
 wherein the first data input terminal is connected to the first inverted output terminal and the second clock terminal, 
 wherein the second data input terminal is connected to the second inverted output terminal, 
 wherein the third data input terminal is connected to the third inverted output terminal and the fourth clock terminal, and 
 wherein the fourth data input terminal is connected to the fourth inverted output terminal. 
 
     
     
       19. The semiconductor device according to  claim 17 ,
 wherein the first D-type flip-flop is configured to output an output signal, 
 wherein the second D-type flip-flop is configured to output a first error signal, 
 wherein the third D-type flip-flop is configured to output an inverted signal of the output signal, 
 wherein the fourth D-type flip-flop is configured to output a second error signal, 
 wherein a first reference potential is supplied to the first comparator, 
 wherein a second reference potential is supplied to the second comparator, and 
 wherein the first reference potential is higher than the second reference potential. 
 
     
     
       20. An electronic device comprising the semiconductor device according to  claim 17 . 
     
     
       21. A semiconductor device comprising:
 a coil configured to generate an induced electromotive force by utilizing electromagnetic induction; 
 a first comparator connected to the coil; 
 a second comparator connected to the coil; 
 a first signal processing circuit comprising a first T-type flip-flop and a second T-type flip-flop connected to the first T-type flip-flop; and 
 a second signal processing circuit comprising a third T-type flip-flop and a fourth T-type flip-flop connected to the third T-type flip-flop, 
 a first inverter circuit between the second comparator and the first signal processing circuit; and 
 a second inverter circuit between the first comparator and the second signal processing circuit, 
 wherein the first T-type flip-flop is further connected to the first comparator and the first inverter circuit, 
 wherein the second T-type flip-flop is further connected to the first inverter circuit, 
 wherein the third T-type flip-flop is further connected to the first comparator and the second inverter circuit, and 
 wherein the fourth T-type flip-flop is further connected to the second inverter circuit. 
 
     
     
       22. The semiconductor device according to  claim 21 ,
 wherein the first comparator comprising a first non-inversion input terminal and a first inversion input terminal, 
 wherein the second comparator comprising a second non-inversion input terminal and a second inversion input terminal, 
 wherein the first T-type flip-flop comprising a first count input terminal, a first output terminal, a first inverted output terminal, and a first inversion reset terminal, 
 wherein the second T-type flip-flop comprises a second count input terminal, a second output terminal, a second inverted output terminal, and a second inversion reset terminal, 
 wherein the third T-type flip-flop comprises a third count input terminal, a third output terminal, a third inverted output terminal, and a third inversion reset terminal, 
 wherein the fourth T-type flip-flop comprises a fourth count input terminal, a fourth output terminal, a fourth inverted output terminal, and a fourth inversion reset terminal, 
 wherein the coil is connected to the first non-inversion input terminal and the second inversion input terminal, 
 wherein the first comparator is connected to the first count input terminal, the second inverter circuit, 
 wherein the second comparator is connected to the third count input terminal, the second inverter circuit, 
 wherein the first inverter circuit is connected to the first inversion reset terminal and the second inversion reset terminal, 
 wherein the second inverter circuit is connected to the third inversion reset terminal and the fourth inversion reset terminal, 
 wherein the first output terminal is connected to the second count input terminal, 
 wherein the third output terminal is connected to the fourth count input terminal. 
 
     
     
       23. The semiconductor device according to  claim 21 ,
 wherein the first T-type flip-flop is configured to output an output signal, 
 wherein the second T-type flip-flop is configured to output a first error signal, 
 wherein the third T-type flip-flop is configured to output an inverted signal of the output signal, 
 wherein the fourth T-type flip-flop is configured to output a second error signal, 
 wherein a first reference potential is supplied to the first comparator, 
 wherein a second reference potential is supplied to the second comparator, and 
 wherein the first reference potential is higher than the second reference potential. 
 
     
     
       24. An electronic device comprising the semiconductor device according to  claim 21 .