Electronic circuit and method for state retention power gating

Abstract

A method and a electronic circuit, the method includes: sending to a switching circuit, to a state retention power gating (SRPG) circuit and to a first power source a control signal indicating that the SRPG circuit should operate in a functional mode; coupling, by the switching circuit, a third power grid to a first power grid; supplying power from the first power source to the SRPG circuit via the first power grid, the switching circuit and the third power grid; supplying power from a second power source to a second circuit via a second power grid; sending to the switching circuit, to the SRPG circuit and to the first power source a control signal indicating that the SRPG circuit should operate in a state retention mode; coupling, by the switching circuit, the third power grid to the second power grid; supplying power from the second power source to the SRPG circuit via the second power grid, the switching circuit and the third power grid; supplying power from the second power source to the second circuit via the second power grid; and storing, by the SRPG state information.

The invention claimed is: 
     
       1. A electronic circuit, comprising:
 a state retention power gating (SRPG) circuit having a functional mode and a state retention mode, said SRPG circuit storing state information when in the state retention mode; 
 a first power grid coupling to the SRPG circuit for providing power from a first power source to the SRPG circuit when the SRPG circuit is in a functional mode; wherein the first power source is arranged to avoid supplying power to the first power grid when the SRPG circuit is in the state retention mode; 
 a second circuit; 
 a second power grid coupling to the second circuit for providing power from a second power source to the second circuit independent from the mode of the SRPG circuit; 
 a switching circuit; 
 a third power grid coupling the SRPG circuit to the switching circuit for providing power received from said switching circuit to the SRPG circuit; and 
 wherein the switching circuit is arranged to couple the third power grid to the first power grid when the SRPG is in the functional mode and to couple the third power grid to the second power grid when the SRPG is in the state retention mode; 
 wherein the electronic circuit further comprising a controller connected to the switching circuit, the SRPG circuit and the first power source, which controller is arranged to generate a control signal that is indicative of a desired operational mode of the SRPG circuit, the desired operational mode being selected from the state retention mode and the functional mode, and to output the control signal to the switching circuit, the SRPG circuit and the first power source. 
 
     
     
       2. The electronic circuit according to  claim 1 , wherein the SRPG circuit is a SRPG flip-flop. 
     
     
       3. The electronic circuit according to  claim 1 , wherein the second circuit is a peripheral. 
     
     
       4. The electronic circuit according to  claim 1 , comprising an integrated circuit; the integrated circuit comprising the SRPG circuit, the second circuit, the first power grid, the second power grid and the third power grid. 
     
     
       5. The electronic circuit according to  claim 1 , wherein the SRPG circuit, when operating in the functional mode, has an average power consumption that exceeds an average power consumption of the second circuit. 
     
     
       6. The electronic circuit according to  claim 1 , wherein the first power grid is coupled to the first power source via N1 inputs, wherein the third power grid is coupled to the switching circuit via N3 inputs, wherein N1 and N3 are integers and N1 is bigger than N3. 
     
     
       7. The electronic circuit according to  claim 6 , wherein N1 is at least ten times bigger than N3. 
     
     
       8. The electronic circuit according to  claim 1 , wherein the third power grid is coupled to the switching circuit via a single input. 
     
     
       9. The electronic circuit according to  claim 1 , wherein the second power source is arranged to alter a level of a second supply voltage supplied to the second power grid based on the operational mode of the SRPG circuit. 
     
     
       10. The electronic circuit according to  claim 1 , wherein the controller is coupled to the second power source, for instructing the second power source to alter a level of a supply voltage provided to the second power grid if an expected duration of the state retention mode is lower than a threshold duration. 
     
     
       11. The electronic circuit according to  claim 1 , wherein the SRPG circuit is a memory unit configured to store state information indicative of a state of a circuit that differs from the memory unit, before the SRPG circuit enters the state retention mode. 
     
     
       12. A method for state retention power gating, the method comprising:
 supplying power from a second power source to a second circuit via a second power grid independent from a mode of a state retention power gating (SRPG) circuit; 
 sending to a switching circuit and to the SRPG circuit a control signal indicating whether the SRPG circuit should operate in a functional mode or in a state retention mode; 
 when said control signal indicates that the SRPG circuit should operate in the functional mode: 
 coupling in response to receiving the control signal, by the switching circuit, a third power grid to a first power grid; 
 supplying power from the first power source to the SRPG circuit via a first path comprising the first power grid, the switching circuit and the third power grid; and 
 operating the SRPG circuit in the functional mode;when said control signal indicates that the SRPG circuit should operate in the state retention mode: 
 coupling in response to receiving the control signal, by the switching circuit, the third power grid to the second power grid and decoupling the third power grid from the first power grid; 
 supplying power from the second power source to the SRPG circuit via a second path comprising the second power grid, the switching circuit and the third power grid; and 
 storing by the SRPG circuit, state information. 
 
     
     
       13. The method according to  claim 12 , wherein the SRPG circuit is a SRPG flip-flop. 
     
     
       14. The method according to  claim 12 , wherein the second circuit is a peripheral. 
     
     
       15. The method according to  claim 12 , wherein the SRPG circuit, when operating in a functional mode, has an average power consumption that exceeds an average power consumption of the second circuit. 
     
     
       16. The method according to  claim 12 , wherein the first power grid is coupled to the first power source via N1 inputs, wherein the third power grid is coupled to the switching circuit via N3 inputs, wherein N1 and N3 are integers and wherein N1 is bigger than N3. 
     
     
       17. The method according to  claim 16 , wherein N1 is at least ten times bigger than N3. 
     
     
       18. The method according to  claim 16 , wherein the third power grid is coupled to the switching circuit via a single input. 
     
     
       19. The method according to  claim 12 , comprising altering a level of a second supply voltage supplied to the second power grid based on the operational mode of the SRPG circuit. 
     
     
       20. The method according to  claim 12 , comprising altering a level of a second supply voltage provided to the second power grid if an expected duration of the state retention mode is lower than a threshold.