Systems, methods and apparatus for superconducting demultiplexer circuits

Abstract

A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.

The invention claimed is: 
     
       1. A superconducting demultiplexer comprising:
 a plurality of switching cells that includes a lead switching cell, a first set of switching cells, and a second set of switching cells, wherein each switching cell in the plurality of switching cells comprises: 
 a signal input end, a first signal output end and a second signal output end; 
 a first Josephson transmission line having a first end and a second end, wherein the first end of the first Josephson transmission line is coupled to the signal input end; 
 a second Josephson transmission line having a first end and a second end, wherein the first end of the second Josephson transmission line is coupled to the first signal output end and the second end of the second Josephson transmission line is coupled to the second output end, and wherein the second end of the first Josephson transmission line is coupled to the second Josephson transmission line at an intersection node; and 
 a flux bias line that is positioned to inductively couple signals to both a first node and a second node on the second Josephson transmission line, wherein the first node on the second Josephson transmission line is located in between the intersection node and the first output end, and wherein the second node on the second Josephson transmission line is located in between the intersection node and the second output end; 
 wherein the input end of the lead switching cell is configured to receive signals from an input signal source, the first output end of the lead switching cell is coupled to the input end of a first switching cell from the first set of switching cells, the second output end of the lead switching cell is coupled to the input end of a second switching cell from the first set of switching cells, the first and the second output ends of both the first and the second switching cells in the first set of switching cells are each coupled to the input end of another respective switching cell in the first set of switching cells, and wherein the input end of each switching cell in the second set of switching cells is coupled to a respective output end of a switching cell in the first set of switching cells. 
 
     
     
       2. The superconducting demultiplexer of  claim 1  wherein at least one output end of at least one switching cell in the second set of switching cells is configured to couple to a programmable device. 
     
     
       3. The superconducting demultiplexer of  claim 2  wherein the programmable device includes an element of a superconducting processor. 
     
     
       4. The superconducting demultiplexer of  claim 3  wherein the programmable device includes an element of a superconducting quantum processor. 
     
     
       5. The superconducting demultiplexer of  claim 2  wherein the programmable device is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, and a superconducting qubit coupler. 
     
     
       6. The superconducting demultiplexer of  claim 1 , further comprising:
 a set of flux storage structures, wherein each flux storage structure is coupled to a respective output end of at least one switching cell in the second set of switching cells, and wherein each flux storage structure comprises: 
 a third Josephson transmission line that includes a first end and a second end, the first end coupled to an output end of at least one switching cell in the second set of switching cells; 
 a storage inductor coupled in series with the third Josephson transmission line; 
 a compound Josephson junction that interrupts the third Josephson transmission line at a node that is located in between the first end and the storage inductor; and 
 a reset line that is positioned to controllably inductively couple signals to the compound Josephson junction. 
 
     
     
       7. The superconducting demultiplexer of  claim 6  wherein at least one storage inductor is positioned to inductively couple signals to at least one programmable device. 
     
     
       8. The superconducting demultiplexer of  claim 6  wherein at least one storage inductor is positioned to inductively couple signals to at least one superconducting loop in a superconducting inductor ladder circuit. 
     
     
       9. The superconducting demultiplexer of  claim 8  wherein at least two storage inductors are each respectively positioned to inductively couple signals to respective ones of at least two loops in a superconducting inductor ladder circuit. 
     
     
       10. The superconducting demultiplexer of  claim 9  wherein the superconducting inductor ladder circuit is positioned to couple signals to at least one programmable device. 
     
     
       11. The superconducting demultiplexer of  claim 10  wherein the at least one programmable device includes an element of a superconducting processor. 
     
     
       12. The superconducting demultiplexer of  claim 11  wherein the at least one programmable device includes an element of a superconducting quantum processor. 
     
     
       13. The superconducting demultiplexer of  claim 12  wherein the at least one programmable device is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, and a superconducting qubit coupler. 
     
     
       14. The superconducting demultiplexer of  claim 1  wherein the same flux bias line is positioned to controllably inductively couple signals to at least two switching cells. 
     
     
       15. A superconducting demultiplexer comprising:
 a plurality of latching qubits that includes a lead latching qubit, a first set of latching qubits, and a second set of latching qubits, wherein each latching qubit in the plurality of latching qubits comprises a qubit loop formed by a loop of material that is superconducting below a critical temperature, and a compound Josephson junction that interrupts the qubit loop, the compound Josephson junction comprising a loop of material that is superconducting below a critical temperature that is interrupted by at least two Josephson junctions; 
 a first set of clock signal lines; 
 a second set of clock signal lines; and 
 at least one control line, wherein each latching qubit in the first and the second sets of latching qubits is positioned to receive signals by inductive coupling to a control line; 
 wherein the lead latching qubit is positioned to receive signals from an input signal source, a first latching qubit in the first set of latching qubits is positioned to inductively couple to the qubit loop of the lead latching qubit and a first clock signal line from the first set of clock signal lines is positioned to controllably inductively couple to the compound Josephson junction of the first latching qubit in the first set of latching qubits, a second latching qubit in the first set of latching qubits is positioned to inductively couple to the qubit loop of the lead latching qubit and a first clock signal line from the second set of clock signal lines is positioned to controllably inductively couple to the compound Josephson junction of the second latching qubit in the first set of latching qubits; and 
 wherein the qubit loop of each latching qubit in the first set of latching qubits is respectively positioned to inductively couple to the qubit loop of three other latching qubits in the plurality of latching qubits, the compound Josephson junction of a first proportion of latching qubits from the first set of latching qubits is positioned to inductively couple to a clock signal line from the first set of clock signal lines, the compound Josephson junction of a second proportion of latching qubits from the first set of latching qubits is positioned to inductively couple to a clock signal line from the second set of clock signal lines, the qubit loop of each latching qubit in the second set of latching qubits is positioned to inductively couple to the qubit loop of a respective one of the latching qubits in the first set of latching qubits, the compound Josephson junction of a first proportion of latching qubits in the second set of latching qubits is positioned to inductively couple to a clock signal line from the first set of clock signal lines, and the compound Josephson junction of a second proportion of latching qubits in the second set of latching qubits is positioned to inductively couple to a clock signal line from the second set of clock signal lines. 
 
     
     
       16. The superconducting demultiplexer of  claim 15  wherein the qubit loop of at least one latching qubit in the second set of latching qubits is configured to couple to a programmable device. 
     
     
       17. The superconducting demultiplexer of  claim 16  wherein the programmable device includes an element of a superconducting processor. 
     
     
       18. The superconducting demultiplexer of  claim 17  wherein the programmable device includes an element of a superconducting quantum processor. 
     
     
       19. The superconducting demultiplexer of  claim 18  wherein the programmable device is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, and a superconducting qubit coupler. 
     
     
       20. The superconducting demultiplexer of  claim 15  wherein at least two latching qubits in the first set of latching qubits are positioned to inductively couple to a same one of the clock signal lines from the first set of clock signal lines. 
     
     
       21. The superconducting demultiplexer of  claim 20  wherein at least two latching qubits in the first set of latching qubits are positioned to inductively couple to a same one of the clock signal lines from the second set of clock signal lines. 
     
     
       22. The superconducting demultiplexer of  claim 15  wherein the first proportion of latching qubits in the first set of latching qubits is approximately fifty percent, the second proportion of latching qubits in the first set of latching qubits is approximately fifty percent, the first proportion of latching qubits in the second set of latching qubits is approximately fifty percent, and the second proportion of latching qubits in the second set of latching qubits is approximately fifty percent. 
     
     
       23. The superconducting demultiplexer of  claim 15  wherein the qubit loop of at least one latching qubit in the second set of latching qubits is positioned to inductively couple to at least one superconducting loop in a superconducting inductor ladder circuit. 
     
     
       24. The superconducting demultiplexer of  claim 23  wherein the qubit loops of at least two respective latching qubits in the second set of latching qubits are positioned to each inductively couple to a respective one of at least two superconducting loops in a superconducting inductor ladder circuit. 
     
     
       25. The superconducting demultiplexer of  claim 24  wherein the superconducting inductor ladder circuit is positioned to couple signals to at least one programmable device. 
     
     
       26. The superconducting demultiplexer of  claim 25  wherein at least one programmable device includes an element of a superconducting processor. 
     
     
       27. The superconducting demultiplexer of  claim 26  wherein at least one programmable device includes an element of a superconducting quantum processor. 
     
     
       28. The superconducting demultiplexer of  claim 27  wherein at least one programmable device is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, and a superconducting qubit coupler. 
     
     
       29. A demultiplexer circuit comprising:
 a first switching cell including an input end and two output ends; 
 a first set of additional switching cells, wherein each switching cell in the first set of additional switching cells includes an input end and two output ends and wherein the first set of additional switching cells includes at least one buffer cell; and 
 an input signal source that is configured to controllably couple input signals to the first switching cell; 
 wherein the first set of additional switching cells is arranged to substantially form a binary tree such that each output end of each switching cell couples to a respective input end of another switching cell and wherein each input end of each switching cell receives at least one input from at least one output of at least one other switching cell, and wherein the input end of the at least one buffer cell receives one respective output end from each of at least two respective switching cells and the two output ends of the at least one buffer cell each couple to the input end of a respective switching cell. 
 
     
     
       30. The demultiplexer of  claim 29  wherein the first set of additional switching cells is arranged in a set of rows such that at least one row includes at least two buffer cells. 
     
     
       31. The demultiplexer of  claim 29  wherein the switching cells are superconducting devices. 
     
     
       32. The demultiplexer of  claim 31 , further comprising a second set of additional switching cells that each include an input end and two output ends, wherein the input end of each switching cell in the second set of additional switching cells is coupled to at least one respective output end of a respective switching cell from the first set of additional switching cells and at least one output end of at least one switching cell in the second set of additional switching cells is configured to couple to a programmable device. 
     
     
       33. The demultiplexer of  claim 32  wherein the programmable device includes an element of a superconducting processor. 
     
     
       34. The demultiplexer of  claim 33  wherein the programmable device includes an element of a superconducting quantum processor. 
     
     
       35. The demultiplexer of  claim 34  wherein the programmable device is selected from the group consisting of: a superconducting flux qubit, a superconducting phase qubit, a superconducting charge qubit, a superconducting hybrid qubit, and a superconducting qubit coupler. 
     
     
       36. A superconducting demultiplexer circuit comprising:
 a network of Josephson transmission lines providing a plurality of superconducting signal paths, wherein each superconducting signal path includes an input end and an output end such that each superconducting signal path shares the same input end and the output end of each superconducting signal path includes a respective compound Josephson junction and a respective superconducting inductor, and wherein each superconducting signal path is positioned to receive control signals by inductive coupling to a plurality of flux bias lines. 
 
     
     
       37. The superconducting demultiplexer circuit of  claim 36  wherein at least one superconducting inductor is positioned to inductively couple to at least one programmable device. 
     
     
       38. The superconducting demultiplexer circuit of  claim 36  wherein at least one superconducting inductor is positioned to inductively couple to a superconducting loop in a superconducting inductor ladder circuit. 
     
     
       39. The superconducting demultiplexer circuit of  claim 38  wherein each superconducting inductor is positioned to inductively couple to a respective one of the superconducting loops in at least one superconducting inductor ladder circuit. 
     
     
       40. A superconducting demultiplexer circuit comprising:
 a binary tree arrangement of superconducting latching qubits wherein each superconducting latching qubit comprises a qubit loop formed by a loop of superconducting material and a compound Josephson junction that interrupts the qubit loop, the compound Josephson junction comprising a closed loop of superconducting material interrupted by at least two Josephson junctions, wherein the qubit loop and the compound Josephson junction form a closed superconducting current path, and wherein the qubit loop of each superconducting latching qubit is positioned to inductively couple at least one input signal and at least two output signals and the compound Josephson junction of each superconducting latching qubit is positioned to receive clock signals by inductive coupling to a clock signal line; and 
 at least one control signal line that is positioned to inductively couple control signals to the respective qubit loops of at least two of the superconducting latching qubits.