US8612906B2ActiveUtilityA1

Apparatus for aiding design of semiconductor device and method

Assignee: NABEYA KENICHIPriority: Mar 31, 2009Filed: Mar 19, 2010Granted: Dec 17, 2013
Est. expiryMar 31, 2029(~2.6 yrs left)· nominal 20-yr term from priority
Inventors:Kenichi Nabeya
H10W 20/495G06F 2119/06G06F 30/33G06F 30/367
30
PatentIndex Score
0
Cited by
11
References
9
Claims

Abstract

An apparatus for aiding a design of a semiconductor device including a plurality of wirings, the apparatus has a display, a memory that stores information corresponding to the wirings, and a processor that obtains a power consumption value of each wiring in reference to the information about the wirings stored in the memory, and displays each of the wirings on the display in a manner that each wiring is distinguishable as to the obtained power consumption value of the each wiring.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An apparatus for aiding a design of a semiconductor device including a plurality of wirings, the apparatus comprising:
 a computer processor that executes instructions to:
 obtain a power consumption value based upon wiring capacitance and signal activities of each wiring, in reference to stored information about the wirings, 
 obtain wiring delay information in reference to stored wiring delay information about the wirings, and 
 display each of the wirings on a display in a manner that each wiring is distinguishable as to the power consumption value of each wiring obtained based upon wiring capacitance and signal activities of each wiring and as to the wiring delay information obtained. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the delay information includes a slack value corresponding to each wiring on basis of the stored wiring delay information about the wirings, and the wirings are displayed on the display in a manner that a wire is distinguishable as to the slack value. 
     
     
       3. The apparatus of  claim 2 , wherein the computer processor further displays the wirings on the display in a manner that a wire which power consumption value is max and slack value is least is distinguishable from other wires. 
     
     
       4. A method of controlling an apparatus for aiding a design of a semiconductor device including a plurality of wirings, the method comprising:
 obtaining, by using a computer, a power consumption value based upon wiring capacitance and signal activities of each wiring, in reference to stored information about the wirings; 
 obtaining wiring delay information in reference to stored wiring delay information about the wirings; and 
 displaying each of the wirings on a display in a manner that each wiring is distinguishable as to the power consumption value of each wiring obtained based upon wiring capacitance and signal activities of each wiring and as to the wiring delay information obtained. 
 
     
     
       5. The method of  claim 4 , wherein the delay information includes a slack value corresponding to each wiring on basis of the stored wiring delay information about the wirings, and the method further comprises displaying the wirings on the display in a manner that a wire is distinguishable as to the slack value. 
     
     
       6. The method of  claim 5 , wherein a wire which power consumption value is max and slack value is least is distinguishably displayed from other wires. 
     
     
       7. A non-transitory computer-readable recording medium storing a program for aiding a design of a semiconductor device including a plurality of wirings, the program causes a computer to execute:
 obtaining a power consumption value based upon wiring capacitance and signal activities of each wiring, in reference to stored information about the wirings; 
 obtaining wiring delay information in reference to stored wiring delay information about the wirings; and 
 displaying each of the wirings on a display in a manner that each wiring is distinguishable as to the power consumption value of each wiring obtained based upon wiring capacitance and signal activities of each wiring and as to the wiring delay information obtained. 
 
     
     
       8. The non-transitory computer-readable recording medium of  claim 7 , wherein the delay information includes a slack value corresponding to each wiring on basis of the stored wiring delay information about the wirings, and the method further comprises displaying the wirings on the display in a manner that a wire is distinguishable as to the slack value. 
     
     
       9. The non-transitory computer-readable recording medium of  claim 8 , wherein the displaying displays the wirings on the display in a manner that a wire which power consumption value is max and slack value is least is distinguishable from other wires.

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