Lateral silicon controlled rectifier structure

Abstract

A lateral silicon controlled rectifier structure includes a P-type substrate; an N-well region in the P-type substrate; a first P + doped region in the N-well region and being connected to an anode; a P-well region in the P-type substrate and bordering upon the N-well region; a first N + doped region formed in the P-well region and separated from the first P + doped region by a spacing distance, the first N + doped region being connected to a cathode; and a gate structure overlying a portion of the P-type substrate between the first P + doped region and the first N + doped region.

What is claimed is: 
     
       1. A lateral silicon controlled rectifier structure, comprising:
 a P-type substrate; 
 an N-well region formed in the P-type substrate; 
 a first P+ doped region formed in the N-well region and being directly connected to an anode; 
 a P-well region formed in the P-type substrate and bordering upon the N-well region; 
 a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being directly connected to a cathode; 
 a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region, wherein the gate structure is right above a junction formed between the N-well region and the P-well region; 
 a second N+ doped region formed in the N-well region, the second N+ doped region being directly connected to the anode and electrically coupled to the first P+ doped region; and 
 a second P+ doped region formed in the P-well region, the second P+ doped region being directly connected to a cathode and electrically coupled to the first N+ doped region. 
 
     
     
       2. The lateral silicon controlled rectifier structure according to  claim 1  wherein the P-type substrate comprises silicon substrate, epitaxial silicon substrate or silicon-on-insulator (SOI) substrate. 
     
     
       3. The lateral silicon controlled rectifier structure according to  claim 1  wherein the gate structure comprises a gate electrode atop a gate dielectric layer, and the gate structure further comprises sidewall spacers. 
     
     
       4. The lateral silicon controlled rectifier structure according to  claim 3  wherein the first P +  doped region and the first N +  doped region align with the sidewall spacers. 
     
     
       5. The lateral silicon controlled rectifier structure according to  claim 3  wherein the gate electrode of the gate structure is coupled to a gate voltage. 
     
     
       6. The lateral silicon controlled rectifier structure according to  claim 1  wherein no field oxide or shallow trench isolation (STI) structure is formed in current path of the lateral silicon controlled rectifier structure. 
     
     
       7. The lateral silicon controlled rectifier structure according to  claim 1  wherein the second P+ doped region is located farther from the N-well region than the first N+ doped region. 
     
     
       8. A lateral silicon controlled rectifier structure, comprising:
 a P-type substrate; 
 an N-well region formed in the P-type substrate; 
 a first P+ doped region formed in the N-well region and being directly connected to an anode; 
 a P-well region formed in the P-type substrate and bordering upon the N-well region; 
 a first N+ doped region formed in the P-well region and separated from the first P+ doped region by a spacing distance, the first N+ doped region being directly connected to a cathode; 
 a gate structure overlying a portion of the P-type substrate between the first P+ doped region and the first N+ doped region, wherein the gate structure is right above a junction formed between the N-well region and the P-well region; 
 a second N+ doped region formed in the N-well region, separated from the first P+ doped region with a first electrical isolation structure, the second N+ doped region being directly connected to the anode and electrically coupled to the first P+ doped region; and 
 a second P+ doped region formed in the P-well region, separated from the first N+ doped region with a second electrical isolation structure, the second P+ doped region being directly connected to a cathode and electrically coupled to the first N+ doped region. 
 
     
     
       9. The lateral silicon controlled rectifier structure according to  claim 8  wherein the P-type substrate comprises silicon substrate, epitaxial silicon substrate or silicon-on-insulator (SOI) substrate. 
     
     
       10. The lateral silicon controlled rectifier structure according to  claim 8  wherein the gate structure comprises a gate electrode atop a gate dielectric layer, and the gate structure further comprises sidewall spacers. 
     
     
       11. The lateral silicon controlled rectifier structure according to  claim 10  wherein the first P+ doped region and the first N+ doped region align with the sidewall spacers. 
     
     
       12. The lateral silicon controlled rectifier structure according to claim  10  wherein the gate electrode of the gate structure is coupled to a gate voltage. 
     
     
       13. The lateral silicon controlled rectifier structure according to  claim 8  wherein no electrical isolation structure is formed in current path of the lateral silicon controlled rectifier structure. 
     
     
       14. The lateral silicon controlled rectifier structure according to  claim 8  wherein the second P +  doped region is located farther from the N-well region than the first N +  doped region.