Noise reduction device and semiconductor device having the same

Abstract

A semiconductor device includes a first terminal for receiving a first signal; a second terminal for receiving a second signal having more restriction than the first signal with respect to a delay upon transmitting to an internal circuit; a first noise reduction circuit; and a second noise reduction circuit. The first noise reduction circuit includes a first Schmitt circuit for receiving the first signal from the first terminal; and an output signal adjusting unit for adjusting an output signal of the first Schmitt circuit when the output signal is maintained for a specific period of time after the output signal is varied. The second noise reduction circuit includes a second Schmitt circuit for receiving the second signal from the second terminal; and an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage.

What is claimed is: 
     
       1. A semiconductor device connected to an internal circuit, comprising:
 a first terminal for receiving a first signal; 
 a second terminal for receiving a second signal; 
 a first noise reduction circuit; and 
 a second noise reduction circuit, 
 wherein said first noise reduction circuit includes 
 a first Schmitt circuit for receiving the first signal from the first terminal and outputting a first output signal; and 
 an output signal adjusting unit for adjusting and outputting a second output signal to the internal circuit when the first output signal is maintained for a specific period of time after the first output signal is varied, and 
 said second noise reduction circuit includes 
 a second Schmitt circuit for receiving the second signal from the second terminal; and 
 an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage applied to the semiconductor device so that the second Schmitt circuit outputs a third output signal to the internal circuit. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein said output signal adjusting unit includes a delay circuit for receiving the first output signal, delaying the first output signal for a specific period of time, and outputting a fourth output signal, and a logic sum circuit for receiving the first output signal and the fourth output signal. 
     
     
       3. The semiconductor device according to  claim 1 , wherein said output signal adjusting unit includes a capacitor element connected between an input terminal and an output terminal of the first Schmitt circuit, or between the input terminal of the first Schmitt circuit and a power source. 
     
     
       4. The semiconductor device according to  claim 1 , wherein said first noise reduction circuit further includes a first low pass filter so that the first signal passes through the first low pass filter and is input into the first Schmitt circuit. 
     
     
       5. The semiconductor device according to  claim 1 , wherein said second noise reduction circuit further includes a second low pass filter so that the second signal passes through the second low pass filter and is input into the second Schmitt circuit. 
     
     
       6. The semiconductor device according to  claim 1 , wherein said second terminal is configured to receive the second signal having a frequency higher than that of the first signal. 
     
     
       7. A noise reduction device to be disposed in a semiconductor device that is connected to an internal circuit, comprising:
 a first noise reduction circuit; and 
 a second noise reduction circuit, 
 wherein said first noise reduction circuit includes 
 a first Schmitt circuit for receiving a first signal from a first terminal disposed in the semiconductor device and outputting a first output signal; and 
 an output signal adjusting unit for adjusting and outputting a second output signal to the internal circuit when the first output signal is maintained for a specific period of time after the first output signal is varied, and 
 said second noise reduction circuit includes 
 a second Schmitt circuit for receiving a second signal from a second terminal disposed in the semiconductor device; and 
 an input signal adjusting unit for adjusting the second signal input to the second Schmitt circuit according to a fluctuation of a power source voltage applied to the semiconductor device so that the second Schmitt circuit outputs a third output signal to the internal circuit. 
 
     
     
       8. The noise reduction device according to  claim 7 , wherein said output signal adjusting unit includes a delay circuit for receiving the first output signal, delaying the first output signal for a specific period of time, and outputting a fourth output signal, and a logic sum circuit for receiving the first output signal and the fourth output signal. 
     
     
       9. The noise reduction device according to  claim 7 , wherein said output signal adjusting unit includes a capacitor element connected between an input terminal and an output terminal of the first Schmitt circuit, or between the input terminal of the first Schmitt circuit and a power source. 
     
     
       10. The noise reduction device according to  claim 7 , wherein said first noise reduction circuit further includes a first low pass filter so that the first signal passes through the first low pass filter and is input into the first Schmitt circuit. 
     
     
       11. The noise reduction device according to  claim 7 , wherein said second noise reduction circuit further includes a second low pass filter so that the second signal passes through the second low pass filter and is input into the second Schmitt circuit.