System and method for contention-free memory access

Abstract

A memory control unit of a turbo code decoder includes a buffer having a plurality of storage slots, a buffer control operatively coupled to the buffer, a router operatively coupled to the buffer control and to a plurality of data sources, and a conflict detection unit operatively coupled to the router, to the buffer control, and to the plurality of data sources. The buffer temporarily stores information intended for storage in a memory bank. The buffer control determines a number of available storage slots in the buffer. The router routes data from the data sources to the buffer control. The conflict detection unit initiates a temporary halt of some of the data sources when the number of available storage slots is insufficient to store all of the data from data sources attempting to access the memory bank.

What is claimed is: 
     
       1. A memory control unit of a turbo code decoder comprising:
 a first buffer having a plurality of storage slots, wherein the first buffer is configured to temporarily store data intended for storage in a memory bank; 
 a buffer control operatively coupled to the first buffer, wherein the buffer control is configured to determine a number of available storage slots in the first buffer; 
 a second buffer operatively coupled to a plurality of data sources, wherein the second buffer is configured to temporarily store data received from the data sources attempting to access the memory bank; 
 a router operatively coupled to the buffer control and to the second buffer, wherein the router is configured to route data from the second buffer to the buffer control; and 
 a conflict detection unit operatively coupled to the router, to the buffer control, and to the second buffer, wherein the conflict detection unit is configured to initiate a temporary halt of the second buffer when the data received from the data sources causes multiple concurrent accesses to the memory bank. 
 
     
     
       2. The memory control unit of  claim 1 , wherein the conflict detection unit is configured to temporarily halt operation of an integer N of concurrent accesses to the memory bank, wherein N is equal to a number of data sources attempting to concurrently access the memory bank minus an integer K, and wherein K is equal to a maximum number of concurrent memory accesses allowed. 
     
     
       3. The memory control unit of  claim 2 , wherein the router is further configured to determine the N attempts to concurrently access the memory bank by the data sources, and wherein data from K of the data sources are forwarded to the buffer control. 
     
     
       4. The memory control unit of  claim 1  further comprising a bypass unit operatively coupled to the buffer control and to the memory bank, wherein the bypass unit is configured to route data from the buffer control unit to the memory bank when the first buffer is empty, and wherein the routed data is not sent to the first buffer prior to the memory bank receiving the routed data. 
     
     
       5. The memory control unit of  claim 1 , wherein the memory control unit operates in synchrony with a sequence of clock cycles, wherein in each clock cycle of the sequence of clock cycles, the buffer control is configured to write data stored in up to L storage slots of the first buffer to the memory bank, wherein L is a number of write ports of the memory bank, and wherein the router is further configured to route data from the second buffer to the buffer control based on priority. 
     
     
       6. The memory control unit of  claim 1 , wherein the second buffer comprises a plurality of buffer units, and wherein the conflict detection unit is configured to assert a specified value on a control signal to initiate the temporary halt for some of the buffer units. 
     
     
       7. The memory control unit of  claim 1 , wherein the second buffer is configured to forward data from up to K of the data sources attempting to concurrently access the memory bank to the router, and wherein K is a maximum number of concurrent allowable memory accesses. 
     
     
       8. The memory control unit of  claim 7 , wherein the second buffer is configured to stall sending some of the data from the data sources attempting to access the memory bank to the router when the number of data sources attempting to concurrently access the memory bank exceeds K. 
     
     
       9. The memory control unit of  claim 1 , wherein the second buffer comprises a plurality of first in first out (FIFO) buffers, wherein each of the FIFO buffers are operatively coupled to a port located at one of the data sources, and wherein the first buffer is accessed in a circular order. 
     
     
       10. The memory control unit of  claim 1 , wherein the conflict detection unit is not configured to send a hold signal directly to the data source units, and wherein each of the data sources are configured to implement a parallel maximum a posteriori probability (MAP) decoding algorithm, and wherein each of the data sources comprise two or more outputs that are operatively coupled to the memory control unit. 
     
     
       11. An information decoder comprising:
 decoders configured to collectively decode a signal according to a decoding algorithm, and to generate data therefrom; 
 an address generator configured to generate memory addresses for the data generated by the decoders; 
 a plurality of memory banks configured to store the data generated by the decoders according to the memory addresses generated by the address generator; and 
 a plurality of memory control units, 
 wherein each of the memory control units are operatively coupled to the decoders, to one of the memory banks, and to the address generator, 
 wherein each of the memory control units having a plurality of storage slots configured to temporarily store data intended for storage in the one of the memory banks, and 
 wherein each of the memory control units are configured to:
 receive data from the decoders; 
 determine a number of concurrent memory accesses to the one of the memory banks attempted by the decoders; 
 determine a maximum number of concurrent allowable memory accesses to the one of the memory banks; and 
 stall a number of memory accesses that exceed the maximum number of concurrent allowable memory accesses for the one of the memory banks, and 
 
 wherein each of the decoders continue to transmit the generated data to the memory control units when the memory control units stall the number of memory accesses to the one of the memory banks. 
 
     
     
       12. The information decoder of  claim 11 , wherein each of the decoders is a soft-in soft-out decoder, wherein each of the memory control units are further configured to:
 determine a number of available storage slots; 
 route data from the decoders to the storage slots; and 
 temporarily stall storing data within the storage slots when the number of available storage slots is insufficient to store all of the data from the decoders attempting to access the one of the memory banks, and wherein the storage slots are operatively arranged in a circular shape. 
 
     
     
       13. The information decoder of  claim 12 , wherein each of the decoders implements a maximum a posteriori probability (MAP) algorithm to decode the signal, and wherein the MAP algorithm is implemented as a Radix decoding architecture of at least Radix-2. 
     
     
       14. The information decoder of  claim 12 , wherein the signal is a turbo code encoded signal, and wherein each of the memory control units are further configured to bypass temporarily storing data within the storage slots by directly storing the data within the one of the memory banks when the storage slots do not store any data. 
     
     
       15. The information decoder of  claim 11 , wherein each of the memory control units is configured to buffer the generated data received from the decoders attempting to access the one of the memory banks and route the generated data received from the decoders based on priority. 
     
     
       16. The information decoder of  claim 15 , wherein each of the memory control units is further configured to forward data from up to K of the decoders attempting to access the one of the memory banks to a router, wherein K is a maximum number of concurrent allowable memory accesses in a single memory control unit, and wherein a total number of memory banks within the information decoder exceeds a total number of decoders within the information decoder. 
     
     
       17. The information decoder of  claim 16 , wherein each of the memory control units is configured to stall data from the decoders within a buffer when a number of the decoders attempting to access the one of the memory banks exceeds K. 
     
     
       18. A method for operating a memory control unit, wherein the method comprises:
 receiving, from a data source, data associated with an integer number N concurrent memory accesses to a memory bank; 
 buffering the received data at a first buffer; 
 determining an integer number K that represents a maximum number of concurrent memory accesses to the memory bank; 
 determining an integer number M of available storage slots in a second buffer; 
 temporarily storing the data associated with the N concurrent memory accesses to the second buffer if M is greater than or equal to N; 
 temporarily storing the data associated with M of the N concurrent memory accesses to the second buffer if N is greater than M; 
 halting the temporary storing of data at the second buffer for the N−M of the N concurrent memory access if N is greater than M; and 
 halting N−K of the N concurrent memory access at the first buffer if N is greater than K. 
 
     
     
       19. The method of  claim 18 , wherein the method further comprises writing data associated with up to L of the N concurrent memory accesses when the second buffer is temporarily storing at least one piece of data, wherein L is a number of write ports of the memory bank, and wherein the second buffer is accessed in a circular way. 
     
     
       20. The method of  claim 18 , wherein the memory control unit operates in synchrony with a sequence of clock cycles, and wherein halting at the first buffer comprises asserting a specified value on a control signal that holds the data for at least one clock cycle at the first buffer. 
     
     
       21. The method of  claim 20 , wherein the first buffer continues to receive data from the data source when halting N−K of the N concurrent memory access at the first buffer, and wherein selecting data from K of the data sources to route to the second buffer is based on priority. 
     
     
       22. The method of  claim 18 , wherein the received data is directly written into the memory bank without being first stored in the second buffer when the second buffer is empty.