Integrated circuit devices having selectively enabled scan paths with power saving circuitry

Abstract

An integrated circuit device includes first and second latches (e.g, D-type flip flops) responsive to a clock signal. Each of the first and second latches respectively includes a data input terminal, a scan input terminal, a scan enable terminal and an output terminal. A combinational logic circuit may be provided, which is configured to receive the signal from the output terminal of the first latch and configured to generate a signal at the data input terminal of the second latch. A scan path is also provided, which is responsive to a scan enable signal. The scan path is configured to selectively pass a signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is active. A power saving switch is also provided. This switch, which is responsive to the scan enable signal, includes a first current carrying terminal electrically coupled to the scan path. The switch is configured to disable the scan path from passing the signal from the output terminal of the first latch to the scan input terminal of the second latch when the scan enable signal is in an inactive state.

That which is claimed is: 
     
       1. An integrated circuit device, comprising:
 a first latch responsive to a clock signal, said first latch comprising a data input terminal, a scan input terminal, a scan enable terminal and an output terminal; 
 a second latch responsive to the clock signal, said second latch comprising a data input terminal, a scan input terminal, a scan enable terminal and an output terminal; 
 a scan path responsive to a scan enable signal, said scan path configured to selectively pass a signal from the output terminal of said first latch to the scan input terminal of said second latch when the scan enable signal is active; and 
 a switch responsive to the scan enable signal, said switch having a first current carrying terminal electrically coupled to said scan path, said switch configured to disable said scan path from passing the signal from the output terminal of said first latch to the scan input terminal of said second latch when the scan enable signal is in an inactive state. 
 
     
     
       2. The device of  claim 1 , wherein the scan enable terminals of said first and second latches are configured to receive the scan enable signal; and wherein said switch is configured to reduce power consumption in said scan path when the scan enable signal switches from an active state to the inactive state. 
     
     
       3. The device of  claim 2 , wherein said scan path comprises at least one delay device having a second current carrying terminal electrically coupled to the first current carrying terminal of said switch. 
     
     
       4. The device of  claim 3 , wherein said switch is an NMOS pull-down transistor. 
     
     
       5. The device of  claim 3 , wherein said scan path comprises:
 an inverter having an input terminal configured to receive the signal from the output terminal of said first latch; and 
 a logic device having a first input configured to receive the scan enable signal and a second input electrically coupled to an output of said inverter. 
 
     
     
       6. The device of  claim 3 , wherein said scan path comprises:
 a plurality of inverters electrically coupled in series, said plurality of inverters comprising a first inverter having an input terminal configured to receive the signal from the output terminal of said first latch; and 
 a logic device having a first input configured to receive the scan enable signal and a second input electrically coupled to an output of a last one of said plurality of inverters. 
 
     
     
       7. The device of  claim 5 , wherein said inverter comprises an NMOS pull-down transistor having a source terminal electrically connected to the first current carrying terminal of said switch. 
     
     
       8. The device of  claim 5 , wherein said logic device has a current carrying terminal electrically connected to the first current carrying terminal of said switch. 
     
     
       9. The device of  claim 5 , wherein said logic device is an AND-type or NAND-type logic gate. 
     
     
       10. The device of  claim 1 , further comprising a combinational logic circuit configured to receive the signal from the output terminal of said first latch, said combinational logic circuit configured to generate a signal at the data input terminal of said second latch. 
     
     
       11. An integrated circuit comprising:
 first and second flip-flops each of said flip-flops comprising a data input, a scan data input, a scan enable input receiving a scan enable signal, and a data output, respectively; and 
 a scan path connected between the data output of the first flip-flop and the scan data input of the second flip-flop, and operating while the scan enable signal is representing a scan mode, 
 wherein the scan path comprises: 
 an inverter connected to a power voltage and a first node, and comprising an input connected to the data output of the first flip-flop and an output; 
 a logic gate comprising a first input receiving the scan enable signal, a second input receiving a signal outputted from the output of the inverter, and an output; 
 a delay circuit connected between the output of the logic gate and the scan data input of the second flip-flop; and 
 a switching device connected between a ground voltage and the first node of the inverter, and controlled by the scan enable signal, and 
 the switching device sets the inverter to a non-operational state while the scan enable signal is representing a data mode. 
 
     
     
       12. The integrated circuit of  claim 11 , wherein the logic gate is an AND gate. 
     
     
       13. The integrated circuit of  claim 11 , wherein the switching device comprises a transistor comprising a drain connected to the first node of the inverter, a source connected to the ground voltage, and a gate connected to the scan enable signal. 
     
     
       14. The integrated circuit of  claim 11 , wherein the inverter comprises first and second transistors sequentially connected in series between the power voltage and the first node, and gates of the first and second transistors are connected to the data output of the first flip-flop. 
     
     
       15. The integrated circuit of  claim 11 , further comprising a combinational logic connected between the data output of the first flip-flop and the data input of the second flip-flop. 
     
     
       16. An integrated circuit comprising:
 first and second flip-flops each of said flip-flops comprising a data input, a scan data input, a scan enable input receiving a scan enable signal, and a data output, respectively; 
 a first delay circuit receiving the scan enable signal and a signal outputted from the data output of the first flip-flop, and outputting a first delay signal; 
 a logic gate comprising a first input receiving the scan enable signal, a second input receiving the first delay signal from the first delay circuit, and an output; and 
 a second delay circuit connected between the output of the logic gate and the scan data input of the second flip-flop, 
 wherein the first delay circuit comprises: 
 a plurality of connection nodes; 
 a plurality of inverters corresponding to the plurality of connection nodes, respectively, connected between a power voltage and the corresponding connection nodes, respectively, and connected in series between the data output of the first flip-flop and the second input of the logic gate; and 
 a plurality of switching devices corresponding to the plurality of connection nodes, respectively, connected between a ground voltage and the corresponding connection nodes, respectively, and controlled by the scan enable signal, and 
 each of the switching devices sets a corresponding inverter to a non-operational state while the scan enable signal is representing a data mode. 
 
     
     
       17. The integrated circuit of  claim 16 , wherein the logic gate is an AND gate. 
     
     
       18. The integrated circuit of  claim 16 , wherein each of the switching devices comprises a MOS transistor comprising a drain connected to the corresponding connection node, a source connected to the ground voltage, and a gate connected to the scan enable signal. 
     
     
       19. The integrated circuit of  claim 16 , further comprising a combinational logic connected between the data output of the first flip-flop and the data input of the second flip-flop.