Audio amplifying circuit with improved noise performance

Abstract

An amplifying circuit includes a first circuit component configured to receive and amplify first and second input voltages to generate an output voltage. The first circuit component is formed by a first amplifier and a second amplifier. A second circuit component is configured to provide a first offset current that is associated with a first input current of the first amplifier. The first offset current compensates for variation in the first input current. A third circuit component is configured to provide a second offset current that is associated with a second input current of the second amplifier. The second offset current compensates for variation in the second input current.

What is claimed is: 
     
       1. An amplifying circuit, comprising:
 a first circuit component configured to receive at first and second input nodes and amplify a first input voltage and a second input voltage, respectively, wherein the first circuit component comprises a first amplifier having a first input current at the first input node and a second amplifier having a second input current at the second input node; 
 a second circuit component configured to provide a first offset current summed with the first input current at the first input node of the first amplifier to compensate for variation in the first input current; and 
 a third circuit component configured to provide a second offset current summed with the second input current at the second input node of the second amplifier to compensate for variation in the second input current; 
 wherein the first offset current is mirrored from a reference current of the first amplifier and the second offset current is mirrored from a reference current of the second amplifier. 
 
     
     
       2. The amplifying circuit of  claim 1 , wherein the first input current has a different value from the second input current. 
     
     
       3. The amplifying circuit of  claim 1 , further comprising: a fourth circuit component configured to provide a reference voltage to the first circuit component. 
     
     
       4. An amplifying circuit, comprising:
 a first circuit component configured to receive at first and second input nodes and amplify a first input voltage and a second input voltage, respectively, wherein the first circuit component comprises a first amplifier having a first input current at the first input node and a second amplifier having a second input current at the second input node; 
 a second circuit component configured to provide a first offset current summed with the first input current at the first input node of the first amplifier to compensate for variation in the first input current; and 
 a third circuit component configured to provide a second offset current summed with the second input current at the second input node of the second amplifier to compensate for variation in the second input current; 
 wherein the second circuit component comprises a first current mirror configured to mirror a first current in generating the first input current, and the third circuit component comprises a second current mirror configured to mirror a second current in generating the second input current. 
 
     
     
       5. The amplifying circuit of  claim 4 , wherein the first amplifier comprises a first pair of bipolar transistors serving as an input stage, which is biased by a first reference current provided by a first MOS transistor, and the first current mirror comprises a first bipolar transistor, a second MOS transistor, a third MOS transistor, and a fourth MOS transistor, wherein the second MOS transistor is configured to provide a second reference current, a source of the second MOS transistor is coupled to an emitter of the first bipolar transistor, the collector of the first bipolar transistor is coupled to a first supply node with a source of the third MOS transistor and a source of the fourth MOS transistor, a base of the first bipolar transistor is coupled to a drain and gate of the third MOS transistor and a gate of the fourth MOS transistor, and a drain of the fourth MOS transistor is coupled to a first input node configured to receive the first input voltage. 
     
     
       6. The amplifying circuit of  claim 5 , wherein the second reference current is half of the first reference current, and the first bipolar transistor is identical to each of the first pair of bipolar transistors. 
     
     
       7. The amplifying circuit of  claim 6 , wherein the first and second reference currents are generated from a same current source. 
     
     
       8. An amplifying circuit, comprising:
 a first circuit component configured to receive at first and second input nodes and amplify a first input voltage and a second input voltage, respectively, wherein the first circuit component comprises a first amplifier having a first input current at the first input node and a second amplifier having a second input current at the second input node; 
 a second circuit component configured to provide a first offset current summed with the first input current at the first input node of the first amplifier to compensate for variation in the first input current; and 
 a third circuit component configured to provide a second offset current summed with the second input current at the second input node of the second amplifier to compensate for variation in the second input current; 
 wherein the first amplifier has a first input node, a third input node and a first output node, and the second amplifier has a second input node, a fourth input node and a second output node, and 
 wherein the first amplifier is configured to receive the first input voltage and the first input current at the first input node, the second amplifier is configured to receive the second input voltage and the second input current at the second input node; the third input node is coupled to the first output node via a first resistor, the fourth input node is coupled to the second output node via a second resistor, the third input node is coupled to the fourth input node via an impedance component, and the amplifying circuit generates an output voltage between the first and second output nodes. 
 
     
     
       9. The amplifying circuit of  claim 8 , wherein the impedance component comprises a resistor. 
     
     
       10. The amplifying circuit of  claim 8 , wherein the impedance component comprises a fourth resistor, a fifth resistor, a sixth resistor and a first capacitor, wherein the fourth and fifth resistors are coupled in series between the third and fourth input nodes, and a common node thereof is coupled to a first supply node via the series coupled sixth resistor and first capacitor. 
     
     
       11. The amplifying circuit of  claim 8 , further comprising a load coupled between the first and second output nodes. 
     
     
       12. An amplifying circuit, comprising:
 a first circuit component configured to receive at first and second input nodes and amplify a first input voltage and a second input voltage, respectively, wherein the first circuit component comprises a first amplifier having a first input current at the first input node and a second amplifier having a second input current at the second input node; 
 a second circuit component configured to provide a first offset current summed with the first input current at the first input node of the first amplifier to compensate for variation in the first input current; 
 a third circuit component configured to provide a second offset current summed with the second input current at the second input node of the second amplifier to compensate for variation in the second input current; and 
 a fourth circuit component configured to provide a reference voltage to the first circuit component; 
 wherein the fourth circuit component comprises a divider having a seventh resistor and an eighth resistor coupled in series between a second supply node and the first supply node, the common node of the seventh and eighth resistors providing the reference voltage via a ninth resistor to the first amplifier and via a tenth resistor to the second amplifier. 
 
     
     
       13. The amplifying circuit of  claim 12 , wherein the fourth circuit component further comprises a low-pass filter configured to filter the reference voltage before supplying to the first circuit component. 
     
     
       14. The amplifying circuit of  claim 12 , wherein the ninth resistor has a same resistance as the tenth resistor. 
     
     
       15. An amplifying circuit, comprising:
 a first circuit component configured to receive at first and second input nodes and amplify a first input voltage and a second input voltage, respectively, wherein the first circuit component comprises a first amplifier having a first input current at the first input node and a second amplifier having a second input current at the second input node; 
 a second circuit component configured to provide a first offset current summed with the first input current at the first input node of the first amplifier to compensate for variation in the first input current; 
 a third circuit component configured to provide a second offset current summed with the second input current at the second input node of the second amplifier to compensate for variation in the second input current; 
 a fourth circuit component configured to provide a reference voltage to the first circuit component; and 
 a second capacitor and a third capacitor, wherein a first node of the second capacitor is coupled to the first input node and a second node of the second capacitor is configured to receive the first input voltage; and a first node of the third capacitor is coupled to the second input node and a second node of the third capacitor is coupled to the first supply node. 
 
     
     
       16. The circuit of  claim 15 , wherein the second capacitor and the third capacitor have a same capacitance. 
     
     
       17. An amplifying circuit, comprising:
 a pair of transistors coupled in a differential configuration; 
 a first current source coupled to source a first reference current to the pair of transistors; 
 a first current sink configured to sink an offset current from a control terminal of one transistor in said pair of transistors; and 
 a second current source coupled to source a second reference current, 
 wherein the first and second reference currents are mirrored currents derived from a third reference current; and 
 wherein the offset current is derived from the second reference current. 
 
     
     
       18. The amplifying circuit of  claim 17 , wherein the offset current is mirrored from the second reference current. 
     
     
       19. An amplifying circuit, comprising:
 a differential amplifier circuit component having a first input voltage node configured to receive an input voltage and a second input voltage node configured to receive a feedback signal and to an output voltage node, wherein said first input voltage node is further configured to receive a first input current; and 
 an offset current generator configured to provide a first offset current that is sunk from said first input voltage node, wherein the first offset current is summed with said first input current at the first input voltage node to compensate for variation present in the first input current; 
 wherein the offset current generator comprises a first current mirror configured to mirror a reference current of the differential amplifier circuit to generate the first offset current. 
 
     
     
       20. The amplifying circuit of  claim 19 , wherein the first current mirror is configured to generate the first offset current from a first reference current. 
     
     
       21. The amplifying circuit of  claim 20 , wherein the differential amplifier circuit is operable responsive to a second reference current, wherein the first and second reference currents are mirrored currents derived from a third reference current.