Low noise amplifier including a single-ended input

Abstract

A low-noise amplifier (LNA) includes an input terminal for receiving an input signal, an output terminal for providing an output signal related to the input signal. The LNA further includes a first transistor having a first source coupled to the input terminal through the first capacitor, a first gate configured to receive a first direct current (DC) bias signal, and a first drain coupled to the output terminal. The LNA also includes a second transistor having a second source coupled to the input terminal through the second capacitor, a second gate configured to receive a second DC bias signal, and a second drain coupled to the output terminal.

What is claimed is: 
     
       1. A low-noise amplifier (LNA) comprising:
 an input node configurable to couple to a transmission line to receive an input signal; 
 an output node; 
 a first capacitor coupled between the input node and a first node; 
 a second capacitor coupled between the input node and a second node; 
 a first resistor coupled to the first node; 
 a second resistor coupled to the second node; 
 a first transistor including a first terminal coupled to the first node through the first resistor, a control terminal configured to receive a first direct current (DC) bias signal, and a second terminal coupled to the output node; and 
 a second transistor including a first terminal coupled to the second node through the second resistor, a control terminal configured to receive a second DC bias signal, and a second terminal coupled to the output node. 
 
     
     
       2. The LNA of  claim 1 , wherein:
 the first capacitor includes a first terminal coupled to the input node and a second terminal coupled to the first node; 
 the second capacitor includes a first terminal coupled to the input node and a second terminal coupled to the second node; and 
 the first terminals of the first and second capacitors are coupled to each other. 
 
     
     
       3. The LNA of  claim 1 , further comprising:
 a first inductor having a first terminal coupled to the first node and a second terminal coupled to a first DC supply node; and 
 a second inductor including a first terminal coupled to the second node and a second terminal coupled to a second DC supply node. 
 
     
     
       4. The LNA of  claim 1 , wherein the first transistor comprises a p-channel metal oxide semiconductor field effect transistor (MOSFET) and the second transistor comprises an re-channel MOSFET. 
     
     
       5. The LNA of  claim 4 , wherein the first transistor and the second transistor are substantially matched and operate as push-pull complementary stages that substantially cancel second-order distortion. 
     
     
       6. The LNA of  claim 1 , wherein the first resistor and the second resistor operate to desensitize on voltage variations between the first and second transistors across process corners. 
     
     
       7. The LNA of  claim 1 , wherein the first node is DC coupled to a first power supply and the second node is DC coupled to a second power supply. 
     
     
       8. A low-noise amplifier (LNA) comprising:
 an input node configured to receive an input signal from a transmission line; 
 an output node; 
 a first capacitor including a first electrode coupled to the input node and a second electrode coupled to a first node; 
 a second capacitor including a first electrode coupled to the input node and a second electrode coupled to a second node; 
 a first transistor circuit including a first terminal, a control terminal configured to receive a first direct current (DC) bias signal, and a second terminal coupled to the output node; 
 a second transistor circuit including a first terminal, a control terminal configured to receive a second DC bias signal, and a second terminal coupled to the output node; 
 a first resistor coupled between the first node and the first terminal of the first transistor circuit; and 
 a second resistor coupled between the second node and the first terminal of the second transistor circuit. 
 
     
     
       9. The LNA of  claim 8 , wherein the first transistor circuit comprises a p-channel metal oxide semiconductor field effect transistor (PMOSFET) circuit and the second transistor comprises an n-channel metal oxide semiconductor field effect transistor (NMOSFET) circuit. 
     
     
       10. The LNA circuit of  claim 9 , wherein the first transistor circuit comprises:
 a first PMOSFET including a source forming the first terminal of the first transistor circuit, the source coupled to the first node, the first PMOSFET further including a gate and a drain; and 
 a second PMOSFET including a source coupled to the drain of the first PMOSFET, a gate, and a drain coupled to the output node. 
 
     
     
       11. The LNA circuit of  claim 10 , wherein the second transistor circuit comprises:
 a first NMOSFET including a source forming the first terminal of the second transistor circuit, the source coupled to the first node, the first NMOSFET further including a gate and a drain; and 
 a second NMOSFET including a source coupled to the drain of the first NMOSFET, a gate, and a drain coupled to the output node. 
 
     
     
       12. The LNA circuit of  claim 11 , further comprising a bias circuit configured to selectively provide the first DC bias signal to the gates of the first and second PMOSFETs and to selectively provide the second DC bias signal to the gates of the first and second NMOSFETs. 
     
     
       13. The LNA circuit of  claim 8 , wherein the first and second transistor circuits have substantially equal on voltages and operate as push-pull complementary stages that substantially cancel second-order distortion. 
     
     
       14. The LNA circuit of  claim 8 ,
 wherein the first and second resistors provide source degeneration for the first and second transistor circuits to reduce sensitivity to variations in the on voltages across process corners. 
 
     
     
       15. A low-noise amplifier (LNA) comprising:
 a first node that is AC coupled to an input node configured to receive an input signal from a transmission line; 
 a second node that is AC coupled to the input node; 
 an output node; 
 a first resistor including a first terminal coupled to the first node and including a second terminal; 
 a second resistor including a first terminal coupled to the second node and including a second terminal; 
 a first transistor circuit including a first terminal coupled to the second terminal of the first resistor, a control terminal configured to receive a first direct current (DC) bias signal, and a second terminal coupled to the output node; and 
 a second transistor circuit including a first terminal coupled to the second terminal of the second resistor, a control terminal configured to receive a second DC bias signal, and a second terminal coupled to the output node; and 
 wherein the first and second transistors operate as push-pull complementary stages that substantially cancel second-order distortion. 
 
     
     
       16. The LNA of  claim 15 , wherein the first resistor and the second resistor operate to desensitize variations in on voltages between the first and second transistors across process corners. 
     
     
       17. The LNA of  claim 15 , wherein:
 the first transistor circuit comprises: 
 a first p-channel metal oxide semiconductor field effect transistor (PMOSFET) including a source forming the first terminal of the first transistor circuit, the source coupled to the first node, the first PMOSFET further including a gate and a drain; and 
 a second PMOSFET including a source coupled to the drain of the first PMOSFET, a gate, and a drain coupled to the output node; and 
 the second transistor circuit comprises: 
 a first n-channel metal oxide semiconductor field effect transistor (NMOSFET) including a source forming the first terminal of the second transistor circuit, the source coupled to the first node, the first NMOSFET further including a gate and a drain; and 
 a second NMOSFET including a source coupled to the drain of the first NMOSFET, a gate, and a drain coupled to the output node. 
 
     
     
       18. The LNA of  claim 17 , further comprising a bias circuit coupled to the gates of the first and second PMOSFETs and to the gates of the first and second NMOSFETs. 
     
     
       19. The LNA of  claim 15 , further comprising:
 a first inductor having a first terminal coupled to the first node and a second terminal coupled to a first DC supply node; and 
 a second inductor including a first terminal coupled to the second node and a second terminal coupled to a second DC supply node. 
 
     
     
       20. The LNA of  claim 15 , wherein the first node is DC coupled to a first power supply and the second node is DC coupled to a second power supply.