System and method of calibrating a phase-locked loop while maintaining lock

Abstract

A method of calibrating a phase-locked loop (PLL) while maintaining lock includes detecting that a control signal to an oscillator in a PLL has exceeded a threshold value while the PLL is locked to an input signal. In response, an operating current of the oscillator is adjusted to return the control signal below the threshold value while maintaining lock of the PLL to the input signal. Adjusting the operating current includes slowly varying an output current of a calibration circuit coupled to the PLL, enabling the PLL to maintain lock to the input signal during adjustment of the operating current.

What is claimed is: 
     
       1. A method comprising:
 detecting that a control signal to an oscillator in a phase-locked loop (PLL) has exceeded a threshold while the PLL is locked to an input signal, wherein detecting that the control signal has exceeded the threshold includes:
 providing the control signal to an analog-to-digital converter (ADC), 
 converting the control signal to a digital value at the ADC, and 
 comparing the digital value to the threshold; 
 
 sending a calibration signal to a calibration circuit based on an output of the ADC; and 
 in response to the detecting, adjusting an operating current of the oscillator to return the control signal below the threshold while maintaining lock of the PLL to the input signal, wherein adjusting the operating current includes slowly varying an output current of the calibration circuit coupled to the PLL to enable the PLL to maintain lock to the input signal during adjustment of the operating current, wherein adjusting the output of the calibration circuit includes adjusting an input current applied to a gate of a first transistor, wherein the gate of the first transistor is coupled to a gate of a second transistor via a resistive element, and wherein a current steering circuit generates a feedback current to partially offset the input current based on a voltage difference across the resistive element. 
 
     
     
       2. The method of  claim 1 , wherein the threshold comprises an upper threshold of the PLL or a lower threshold of the PLL. 
     
     
       3. The method of  claim 1 , further comprising performing an initial calibration of the PLL prior to attaining lock of the PLL to the input signal by sending an initial calibration signal to a first current source coupled to the PLL to set an initial calibration current of the PLL, wherein a second current source coupled to the PLL is responsive to the control signal to provide a tuning current, and wherein the initial calibration current enables the PLL to initially lock to the input signal at a value of the control signal that is below the threshold. 
     
     
       4. The method of  claim 3 , wherein the operating current comprises the initial calibration current, the tuning current, and the output current of the calibration circuit. 
     
     
       5. The method of  claim 1 , wherein the current steering circuit at least partially throttles a voltage applied at the gate of the second transistor. 
     
     
       6. The method of  claim 5 , wherein the current steering circuit comprises a first current source serially coupled to a second current source via a node, the first current source responsive to a first voltage at a first terminal of the resistive element to output a first current to the node and the second current source responsive to a second voltage at a second terminal of the resistive element to input a second current from the node, and wherein the feedback current comprises a difference between the first current and the second current. 
     
     
       7. The method of  claim 1 , wherein the detecting and the adjusting are performed at a processor integrated into an electronic device. 
     
     
       8. An apparatus comprising:
 a phase-locked loop (PLL) including an oscillator; and 
 a calibration circuit configured to slowly vary an output current supplied to the PLL in response to a determination that a control signal to the oscillator has exceeded a threshold, 
 wherein the calibration circuit comprises:
 a first transistor to receive an input current at a first gate; 
 a second transistor having a second gate coupled to the first gate via a resistive element; and 
 a current steering circuit to generate a feedback current to partially offset the input current based on a voltage difference across the resistive element, 
 
 wherein slowly varying the output current adjusts an operating current of the oscillator to return the control signal below the threshold, and 
 wherein slowly varying the output current enables the PLL to maintain lock to an input signal during adjustment of the operating current. 
 
     
     
       9. The apparatus of  claim 8 , further comprising an analog-to-digital converter (ADC) to receive the control signal. 
     
     
       10. The apparatus of  claim 9 , further comprising logic to send a calibration signal to the calibration circuit based on a digital output of the ADC. 
     
     
       11. The apparatus of  claim 8 , further comprising:
 a first current source to supply an initial calibration current to the PLL prior to the lock of the PLL to the input signal; and 
 a second current source responsive to the control signal to provide a tuning current to the PLL, 
 wherein the operating current comprises the initial calibration current, the tuning current, and the output current supplied by the calibration circuit. 
 
     
     
       12. The apparatus of  claim 8 , wherein the current steering circuit comprises:
 a first current source; and 
 a second current source serially coupled to the first current source via a node, 
 wherein the first current source is responsive to a first voltage at a first terminal of the resistive element to output a first current to the node, 
 wherein the second current source is responsive to a second voltage at a second terminal of the resistive element to input a second current from the node, and 
 wherein the feedback current comprises a difference between the first current and the second current. 
 
     
     
       13. The apparatus of  claim 8 , further comprising a capacitor coupled to the resistive element. 
     
     
       14. The apparatus of  claim 8 , integrated in at least one semiconductor die. 
     
     
       15. The apparatus of  claim 8 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the PLL is integrated. 
     
     
       16. An apparatus comprising:
 a phase-locked loop (PLL) including an oscillator; and 
 means for calibrating the PLL by slowly varying an output current supplied to the PLL in response to a determination that a control signal to the oscillator has crossed a threshold, 
 wherein the means for calibrating comprises:
 a first transistor to receive an input current at a first gate; 
 a second transistor having a second gate coupled to the first gate via a resistive element; and 
 means for steering a feedback current to partially offset the input current based on a voltage difference across the resistive element, 
 
 wherein slowly varying the output current adjusts an operating current of the oscillator, and 
 wherein slowly varying the output current enables the PLL to maintain lock to an input signal during adjustment of the operating current. 
 
     
     
       17. The apparatus of  claim 16 , further comprising means for converting the control signal to a corresponding digital value. 
     
     
       18. The apparatus of  claim 17 , further comprising means for sending a calibration signal to the means for calibrating based on an output of the means for converting. 
     
     
       19. The apparatus of  claim 16 , integrated in at least one semiconductor die. 
     
     
       20. The apparatus of  claim 16 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the means for calibrating is integrated.