ESD power clamp using a low-voltage transistor to clamp a high-voltage supply in a mixed-voltage chip

Abstract

An electro-static-discharge (ESD) protection circuit is a power clamp between a high-voltage power supply VDDH and a ground. The power clamp protects high-voltage transistors in a first core and low-voltage transistors in a second core using a low-voltage clamp transistor. The low-voltage transistors have lower power-supply and snap-back voltages than the high-voltage transistors. Trigger circuits are triggered when an ESD pulse is detected on VDDH. One trigger circuit enables a gate of the low-voltage clamp transistor. A series of diodes connected between VDDH and a drain of the clamp transistor prevents latch up or snap-back during normal operation. During an ESD pulse, the series of diodes is briefly bypassed by a p-channel bypass transistor when a second trigger circuit activates an initial trigger transistor which pulses the gate of the p-channel bypass transistor low for a period of time set by an R-C network in the second trigger circuit.

I claim: 
     
       1. A mixed-voltage electro-static-discharge (ESD) protection circuit comprising:
 a high-voltage core having high-voltage transistors that have a high snap-back breakdown voltage, the high-voltage transistors being powered by a high-voltage power supply; 
 a low-voltage core having low-voltage transistors that have a lower snap-back breakdown voltage than the high snap-back breakdown voltage; the low-voltage transistors being powered by a low-voltage power supply that has a lower voltage than the high-voltage power supply; 
 a first trigger circuit coupled to the high-voltage power supply that drives high-voltage transistors in the high-voltage core, the first trigger circuit activating a first gate when an ESD pulse is detected on the high-voltage power supply; 
 a second trigger circuit coupled to the high-voltage power supply, the second trigger circuit activating a second gate when the ESD pulse is detected on the high-voltage power supply; 
 a clamp transistor that is connected to shunt current from a drain node to a ground node in response to the first gate, wherein the clamp transistor is a low-voltage transistor having the lower snap-back breakdown voltage; 
 an initial shunt bypass that is activated by the second gate to shunt current from the high-voltage power supply to the drain node in response to the second trigger circuit; and 
 a low-voltage transistor protector coupled between the high-voltage power supply and the drain node, for generating a voltage drop to the drain node, wherein the voltage drop is sufficient to prevent the drain node from reaching the lower snap-back breakdown voltage when no ESD pulse is detected; 
 
       whereby the clamp transistor is biased to the lower snap-back breakdown voltage by the initial shunt bypass to protect low-voltage transistors in the low-voltage core, and the clamp transistor is protected by the low-voltage transistor protector during normal operation. 
     
     
       2. The mixed-voltage ESD protection circuit of  claim 1  wherein the initial shunt bypass is activated for a period of time determined by a time constant of the second trigger circuit;
 wherein the period of time is sufficient to raise a voltage of the drain node to the lower snap-back breakdown voltage to initiate breakdown in the clamp transistor. 
 
     
     
       3. The mixed-voltage ESD protection circuit of  claim 2  wherein the period of time is insufficient to reach thermal breakdown of the clamp transistor. 
     
     
       4. The mixed-voltage ESD protection circuit of  claim 1  wherein the clamp transistor comprises an n-channel transistor of a low-voltage type for use with the low-voltage power supply and not for use with the high-voltage power supply. 
     
     
       5. The mixed-voltage ESD protection circuit of  claim 4  wherein the low-voltage transistor protector comprises a series of diodes connected between the high-voltage power supply and the drain node. 
     
     
       6. The mixed-voltage ESD protection circuit of  claim 5  wherein the initial shunt bypass comprises:
 a bypass transistor coupled to conduct bypass current between a tap node within the series of diodes and the drain node in response to a bypass gate node; 
 a bypass-trigger resistor coupled to the bypass gate node; 
 an initial trigger transistor coupled to conduct current from the bypass gate node to the ground node in response to the second gate from the second trigger circuit. 
 
     
     
       7. The mixed-voltage ESD protection circuit of  claim 6  wherein the bypass transistor comprises a p-channel transistor of the low-voltage type for use with the low-voltage power supply and not for use with the high-voltage power supply;
 wherein the initial trigger transistor comprises an n-channel transistor of the low-voltage type. 
 
     
     
       8. The mixed-voltage ESD protection circuit of  claim 7  further comprising:
 a reverse diode connected to conduct current from the tap node to the high-voltage power supply. 
 
     
     
       9. The mixed-voltage ESD protection circuit of  claim 8  wherein the low-voltage power supply is connected to the bypass-trigger resistor in the initial shunt bypass. 
     
     
       10. The mixed-voltage ESD protection circuit of  claim 8  wherein the initial shunt bypass further comprises a diode connected in series with the bypass-trigger resistor between the bypass gate node and the high-voltage power supply. 
     
     
       11. The mixed-voltage ESD protection circuit of  claim 7  wherein the first trigger circuit comprises:
 a first resistor coupled between the ground node and the first gate node; and 
 a first capacitor coupled between the first gate node and the high-voltage power supply, the first capacitor having a thicker insulating oxide layer than a thickness of a gate oxide of the low-voltage transistors; 
 
       wherein the second trigger circuit comprises:
 a second resistor coupled between the ground node and the second gate node; and 
 a second capacitor coupled between the second gate node and the high-voltage power supply, the second capacitor having the thicker insulating oxide layer than the thickness of the gate oxide of the low-voltage transistors. 
 
     
     
       12. The mixed-voltage ESD protection circuit of  claim 7  wherein the first trigger circuit comprises:
 a first resistor coupled between the ground node and the first gate node; 
 a first protector having a series of one or more diodes between the high-voltage power supply and a first protected node; and 
 a first capacitor coupled between the first gate node and the first protected node, the first capacitor having an insulating oxide layer that is a same thickness of a gate oxide of the low-voltage transistors; 
 
       wherein the second trigger circuit comprises:
 a second resistor coupled between the ground node and the second gate node; 
 a second protector having a series of one or more diodes between the high-voltage power supply and a second protected node; and 
 a second capacitor coupled between the second gate node and the second protected node, the second capacitor having an insulating oxide layer having the same thickness of the gate oxide of the low-voltage transistors. 
 
     
     
       13. The mixed-voltage ESD protection circuit of  claim 7  wherein the high-voltage transistors use a larger than minimum transistor gate length;
 wherein the low-voltage transistors use a minimum transistor gate length and have a lower snap-back breakdown voltage than the high snap-back breakdown voltage. 
 
     
     
       14. A power clamp comprising:
 a high power supply node for powering high-voltage transistors; 
 a low power supply node for powering low-voltage transistors; 
 wherein a higher power-supply voltage is applied to the high power supply node than to the low power supply node; 
 wherein low-voltage transistors have a lower snap-back voltage than a higher snap-back voltage of the high-voltage transistors; 
 a ground node; 
 a first trigger for activating a first gate node when an electro-static-discharge (ESD) occurs across the high power supply node and the ground node; 
 a second trigger for activating a second gate node when the ESD occurs across the high power supply node and the ground node; 
 a clamp transistor having a drain connected to a drain node, a source and a substrate connected to the ground node, and a gate connected to the second gate node; 
 a plurality of diodes connected in series between the high power supply node and the drain node, and having an intermediate tap node; 
 a bypass transistor having a drain connected to the drain node, a gate connected to a bypass gate node, and a source and a substrate connected to the intermediate tap node; 
 a bypass-trigger resistor that sources current to the bypass gate node; and 
 an initial trigger transistor having a drain connected to the bypass gate node, a gate connected to the second gate node, and a source and a substrate connected to the ground node. 
 
     
     
       15. The power clamp of  claim 14  wherein the initial trigger transistor and the clamp transistor are n-channel transistors and the bypass transistor is a p-channel transistor, wherein the n-channel transistors and the p-channel transistors have a thin oxide. 
     
     
       16. The power clamp of  claim 14  wherein the bypass-trigger resistor is connected to the low power supply node. 
     
     
       17. The power clamp of  claim 14  wherein the bypass-trigger resistor is connected to a trigger-supply node;
 further comprising: 
 a trigger-supply diode connected to conduct current from the high power supply node to the trigger-supply node. 
 
     
     
       18. The power clamp of  claim 14  wherein a time constant of the second trigger is shorter than a time constant of the first trigger. 
     
     
       19. The power clamp of  claim 14  wherein thermal failure of the low-voltage transistors occurs when the higher snap-back voltage of the high-voltage transistors is applied to the low-voltage transistors. 
     
     
       20. A mixed-supply power protection device comprising:
 high-voltage power supply means for powering high-voltage transistors having a high snap-back breakdown voltage; 
 low-voltage power supply means for powering low-voltage transistors having a lower snap-back breakdown voltage than the high snap-back breakdown voltage; 
 wherein the low-voltage power supply means carries a lower voltage than the high-voltage power supply means; 
 first trigger means for activating a first trigger signal when an electro-static-discharge (ESD) pulse is detected on the high-voltage power supply means; 
 second trigger means for activating a second trigger signal when an electro-static-discharge (ESD) pulse is detected on the high-voltage power supply means; 
 clamp transistor means for shunting current from a drain node to a ground node in response to the first trigger signal, wherein the clamp transistor means is a low-voltage transistor having the lower snap-back breakdown voltage; 
 initial shunt bypass means for shunting current from the high-voltage power supply means to the drain node in response to the second trigger signal; and 
 low-voltage transistor protector means, coupled between the high-voltage power supply means and the drain node, for generating a protective voltage drop to the drain node, wherein the protective voltage drop is sufficient to prevent the drain node from reaching the lower snap-back breakdown voltage when no ESD pulse is detected.