Semiconductor device

Abstract

A semiconductor device includes an active region defined by a device isolation layer and including first and second sections or regions, a gate electrode extending in a first direction across the active region over a channel between the first region and the second region and including at least one first gate tab protruding in a second direction toward the first region, and first and second contact plugs. The first gate tab covers and extends along a boundary between the active region and the device isolation layer. The first contact plug is disposed over the first region, the second contact plug is disposed over the second region, and the second contact plug has an effective width, as measured in the first direction, greater than that of the first contact plug.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a substrate, and a device isolation layer of electrically insulating material disposed at an upper portion of the substrate and delimiting an active region of the substrate; 
 a gate electrode extending across the active region such that a first section of the active region lies to one side of the gate electrode and a second section of the active region lies to the other side of the gate electrode, 
 the gate electrode having a linear main section extending longitudinally across the active region in a first direction, and at least one first gate tab protruding from the linear main section in a second direction, different from the first direction, toward the first section of the active region, and 
 the first gate tab covering a boundary between the active region and the device isolation layer; 
 a first electrically conductive contact plug disposed on the first section of the active region; and 
 a second electrically conductive contact plug disposed on the second section of the active region, and 
 wherein the first contact plug spans a first width of the active region in the first direction, the second contact plug spans a second width of the second section of the active region in the first direction, and the second width is greater than the first width. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein at least part of one end of the second contact plug is juxtaposed in the second direction with at least part of the first gate tab. 
     
     
       3. The semiconductor device of  claim 1 , wherein the at least one first gate tab comprises two first gate tabs are each disposed over a respective boundary between the active region and the device isolation layer, and the first contact plug is interposed between regions occupied by projecting the first gate tabs in the second direction. 
     
     
       4. The semiconductor device of  claim 1 , wherein the first section of the active region and the second section of the region are a drain region and a source region, respectively. 
     
     
       5. The semiconductor device of  claim 1 , wherein the gate electrode also has at least one second gate tab protruding from the linear main section in a direction toward the second section of the active region. 
     
     
       6. The semiconductor device of  claim 5 , wherein the second gate tab has a cross-sectional area, in a plane parallel to an upper surface of the substrate, smaller than that of the first gate tab. 
     
     
       7. The semiconductor device of  claim 5 , wherein the second gate tab has a width in the first direction that decreases in a direction away from the linear main section of the gate electrode, and at is longest over a boundary between the active region and the device isolation layer. 
     
     
       8. The semiconductor device of  claim 1 , wherein at least one of the first contact plug and the second contact plug is discontinuous so as to comprises a plurality of sub-contact plugs spaced from each other in the first direction. 
     
     
       9. The semiconductor device of  claim 8 , wherein each of the first contact plug and the second contact plug is discontinuous so as to comprises a number of sub-contact plugs spaced from each other in the first direction, and the number of the sub-contact plugs constituting the first contact plug is greater than the number of the sub-contact plugs constituting the second contact plug. 
     
     
       10. The semiconductor device of  claim 1 , wherein the device isolation layer delimits a plurality of active regions of the substrate, the active regions each being elongated in the second direction and disposed parallel to each other,
 the device comprises a plurality of the gate electrodes disposed parallel to each other, the linear main sections of each of the gate electrodes extending in the first direction across all of the active regions such that each of active regions has a plurality of at least one of the first sections and the second sections, 
 each of the first sections constituting a drain region and each of the second sections constituting a source region, and 
 transistors of the device are constituted by the gate electrodes, and adjacent ones of the transistors are constituted by a common one of the first and second sections of the active region. 
 
     
     
       11. The semiconductor device of  claim 10 , wherein the first gate tabs of one of each respective pair of the gate electrodes respectively adjoin the first gate tabs of the other of the gate electrodes of the respective pair. 
     
     
       12. A sub-word line driving circuit comprising the semiconductor device as claimed in  claim 1 , and wherein the semiconductor device comprises a p-type metal-oxide semiconductor (PMOS) transistor. 
     
     
       13. The sub-word line driving circuit of  claim 12 , further comprising a selection signal receiving unit electrically connected to one of source and drain electrodes of the PMOS transistor, a sub-word line electrically connected to the other of the source and drain electrodes of the PMOS transistor, and a main word line electrically connected to the gate electrode of the PMOS transistor. 
     
     
       14. A semiconductor device comprising:
 a substrate, and a device isolation layer of electrically insulating material disposed at an upper portion of the substrate and delimiting an active region of the substrate; 
 a gate electrode extending over the active region such that a first section of the active region lies to one side of the gate electrode and a second section of the active region lies to the other side of the gate electrode, and 
 the gate electrode having a linear main section and at least one first gate tab protruding from the main linear section over a peripheral edge of the active region; and 
 contact plugs disposed on the first and second sections, respectively, 
 wherein the cross-sectional area of the contact plug disposed on the first section of the active region, as taken in a plane parallel to an upper surface of the substrate, is larger than that of the contact plug disposed on the second section of the active region. 
 
     
     
       15. The semiconductor device of  claim 14 , wherein the linear main section of the gate electrode extends longitudinally in a first direction, and the gate electrode is asymmetrical about an axis extending in the first direction and bisecting the linear main section of the gate electrode. 
     
     
       16. A semiconductor device comprising:
 a substrate, and a device isolation layer of electrically insulating material disposed at an upper portion of the substrate and delimiting at least one active region of the substrate, and wherein the active region includes a source region and a drain region; 
 at least one electrode disposed on the substrate, each said electrode constituting at least one gate electrode, 
 each said gate electrode having a linear main section extending longitudinally across the at least one active region in a first direction, and at least one first gate tab protruding from one side of the linear main section in a second direction, different from the first direction, over and along a boundary between a said active region and the device isolation layer, 
 and each said first gate tab disposed adjacent one of said source and drain regions; 
 an interlayer insulating layer disposed on the substrate and covering the at least one active region and the device isolation layer; 
 at least one first electrically conductive contact plug extending through the interlayer insulating layer, and each said first contact plug extending upright on a respective one of said one of said source and drain regions; and 
 at least one second electrically conductive contact plug extending through the insulating layer, and each said second contact plug extending upright on a respective one of the other of said source and drain regions, and 
 wherein the linear main section of each said gate electrode extends between the first and second contact plugs of at least one respective pair thereof, and each of the second contact plugs of a said pair thereof is larger than the first contact plug of said pair. 
 
     
     
       17. The semiconductor device of  claim 16 , further comprising a gate insulating layer interposed between the at least one electrode and the active region across which it extends. 
     
     
       18. The semiconductor device of  claim 17 , wherein each said first contact plug extends upright on a respective one of said drain regions, and the semiconductor device comprises a p-type metal-oxide semiconductor (PMOS) transistor. 
     
     
       19. The semiconductor device of  claim 18 , wherein at least one side of each said electrode extends straight across the at least one active region. 
     
     
       20. The semiconductor device of  claim 18 , wherein each said gate electrode also has at least one second gate tab protruding from the other side of the linear main section thereof in the second direction over and along the boundary between the active region and the device isolation layer, and
 for each pair of the first and second gate tabs which extend over and along a said boundary between the active region and the device isolation layer, the second gate tab has a cross-sectional area, in a plane parallel to an upper surface of the substrate, smaller than that of the first gate tab.