Processor and arithmatic operation method

Abstract

A processor has a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address. The processor determines, when a target logical address accessed by one of threads is translated to the physical address, whether an entry corresponding to the target logical address is present in the first table, the target logical address is of a page accessed by a program. The processor determines, when the entry corresponding to the target logical address is not present in the first table, whether the target logical address has been accessed during the running of the program. The processor delays, when the target logical address has not yet been accessed, the process of reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread.

What is claimed is: 
     
       1. A processor in which a plurality of threads operate, the processor comprising:
 a first table including an entry that associates a logical address with a physical address of a page that manages a virtual space address; 
 a first determination section that determines, when a target logical address that is accessed by one of a plurality of threads is translated to a physical address, whether an entry corresponding to the target logical address is present in the first table, whereby the target logical address is of a page accessed by a running program; 
 a second determination section that determines, when the entry corresponding to the target logical address is determined not to be present in the first table, whether the target logical address has been accessed during the running of the program; and 
 a delay control section that
 delays, when it is determined that the target logical address has not yet been accessed, a process of transmitting a request for reading the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread, wherein the predetermined time is a time that is set in advance by the delay control section, and 
 transmits the request without delay of the predetermined time, when it is determined that the target logical address has been accessed. 
 
 
     
     
       2. The processor according to  claim 1 , the processor further comprising:
 a second table including a logical address of an entry deleted from the first table; 
 wherein when the target logical address is not present in the second table, the second determination section determines that the target logical address has not yet been accessed. 
 
     
     
       3. The processor according to  claim 1 , wherein after request data related to a reading by the delay control section is saved in a save area for a predetermined time, the delay control section transmits the request data. 
     
     
       4. The processor according to  claim 1 , wherein when the number of entries in the first table agrees with an upper limit of entries to be registered in the first table, the oldest entry registered in the first table is deleted, and a logical address indicated by the oldest entry is registered in a second table. 
     
     
       5. A device including the processor according to  claim 1 . 
     
     
       6. The processor according to  claim 1 , wherein the delay time is a clock number. 
     
     
       7. The processor according to  claim 1 , wherein the predetermined delay time set in advance is a constant time. 
     
     
       8. An arithmetic operation method for a processor in which a plurality of threads operate, the method comprising:
 determining, when a target logical address that is accessed by one of the plurality of threads is translated to a physical address, whether an entry corresponding to the target logical address of a page accessed by a running program is present in a first table included in the processor; 
 determining, when the entry corresponding to the target logical address is determined not to be present in the first table, whether the target logical address has been accessed during the running of the program; and 
 delaying, when it is determined that the target logical address has not yet been accessed during the running of the program, transmitting a request for a reading of the entry corresponding to the target logical address from a page table into the first table by a predetermined time to thereby delay the one thread that accesses the target logical address, wherein the predetermined time is a delay time set in advance, and 
 transmitting the request without delay of the predetermined time, when it is determined that the target logical address has been accessed. 
 
     
     
       9. The method according to  claim 8 ,
 wherein the processor includes a second table, the second table including a logical address of an entry deleted from the first table; and 
 wherein the determining whether the target logical address has been accessed includes determining that the target logical address has not yet been accessed when the target logical address is not present in the second table. 
 
     
     
       10. The method according to  claim 8 , wherein the reading of the entry corresponding to the target logical address includes:
 after request data related to the reading process is saved in a save area for a predetermined time, transmitting the request data. 
 
     
     
       11. The method according to  claim 8 , wherein when the number of entries in the first table agrees with an upper limit of entries to be registered in the first table, the oldest entry registered in the first table is deleted, and a logical address indicated by the oldest entry is registered in a second table. 
     
     
       12. The method according to  claim 8 , wherein the delay time is a clock number.