Memory cell

Abstract

Methods, and circuits, are disclosed for operating a programmable memory device. One method embodiment includes storing a value as a state in a first memory cell and as a complementary state in a second memory cell. Such a method further includes determining the state of the first memory cell using a first self-biased sensing circuit and the complementary state of the second memory cell using a second self-biased sensing circuit, and comparing in a differential manner an indication of the state of the first memory cell to a reference indication of the complementary state of the second memory cell to determine the value.

What is claimed is: 
     
       1. A circuit for reading a programmable memory cell, comprising:
 a first transistor having a source terminal connected to a ground reference potential; 
 a second transistor having a source terminal connected to a drain terminal of the first transistor, and a gate terminal connected to a power supply voltage; 
 a third transistor having a gate terminal connected to a drain terminal of the second transistor and a source terminal connected to a gate terminal of the first transistor; 
 a fourth transistor having a drain terminal connected to the source terminal of the third transistor, and a source terminal being selectably connected to the programmable memory cell; 
 a fifth transistor having a gate connected to the ground reference potential, a source terminal connected to a pumped voltage source of greater magnitude than the power supply voltage, and a drain terminal connected to a drain terminal of the third transistor; and 
 a sixth transistor having a gate connected to the ground reference potential, a source terminal connected to the pumped voltage source, and a drain terminal connected to a drain terminal of the second transistor, 
 wherein the fourth transistor has a gate terminal connected to a read control signal, the read control signal being driven towards a magnitude of the pumped voltage source during reading the programmable memory cell. 
 
     
     
       2. The circuit of  claim 1 , wherein the first, second, third, and fourth transistors are n-type metal oxide semiconductor (NMOS) field effect transistors (FETs), and the fifth and sixth transistors are p-type metal oxide semiconductor (PMOS) FETs. 
     
     
       3. The circuit of  claim 2 , wherein the fifth and sixth transistors are long channel PMOS FETs. 
     
     
       4. The circuit of  claim 1 , wherein the fifth and sixth transistors are long channel p-type metal oxide semiconductor (PMOS) FETs formed of a number of short channel PMOS FETs connected in series drain-to-source, each short channel PMOS FET having a gate connected to the ground reference potential. 
     
     
       5. The circuit of  claim 4 , wherein each short channel PMOS FETs has a programmable link arranged to short a drain terminal to a source terminal so that the number of short channel PMOS FETs connected in series can be programmed. 
     
     
       6. A method for operating the circuit of  claim 4 , comprising:
 driving the read control signal of the circuit of  claim 4  towards a magnitude of the pumped voltage source; 
 connecting the source terminal of the fourth transistor to a programmable volume of the programmable memory cell to create a current path from the pumped voltage source through the programmable volume to the ground reference potential; and 
 maintaining approximately a threshold voltage of the first transistor at the source of the fourth transistor, the voltage at the source of the fourth transistor being slightly above or below the threshold voltage based on the resistance of the programmable volume. 
 
     
     
       7. The circuit of  claim 1 , wherein the programmable memory cell includes a programmable volume, and
 wherein the source terminal of the fourth transistor is connected in series with the programmable volume of the programmable memory cell through a selected access device. 
 
     
     
       8. The circuit of  claim 7 , wherein the selected access device is a seventh transistor having a gate connected to a word line associated with the programmable memory cell, the seventh transistor arranged to complete a current path between the pumped voltage source and the ground reference potential through a phase change material via a source terminal and a drain terminal of the seventh transistor. 
     
     
       9. The circuit of  claim 1 , further comprising an output terminal connected to the drain terminal of the third transistor. 
     
     
       10. A circuit for reading a programmable memory cell, comprising:
 a first transistor having a first terminal connected to a reference potential; 
 a second transistor having a first terminal connected to a second terminal of the first transistor, and a gate terminal connected to a first voltage source; 
 a third transistor having a gate terminal directly connected to a second terminal of the second transistor, and a first terminal connected to a gate terminal of the first transistor; 
 a fourth transistor having a first terminal selectably connected to the programmable memory cell, and a second terminal connected to the first terminal of the third transistor; 
 a bias current source connected to a drain terminal of the third transistor; and 
 a current source connected to a drain terminal of the second transistor. 
 
     
     
       11. The circuit of  claim 10 , wherein the bias current source comprises a fifth transistor having a gate connected to the reference potential, a first terminal connected to a second voltage source having a greater voltage magnitude than the first voltage source, and a second terminal connected to the second terminal of the third transistor. 
     
     
       12. The circuit of  claim 11 , wherein the fifth transistor is a long channel p-type metal oxide semiconductor (PMOS) field effect transistor (FET). 
     
     
       13. The circuit of  claim 12 , wherein the long channel PMOS FET comprises a plurality of short channel PMOS FETs connected in series drain-to-source, each short channel PMOS FET having a gate connected to the reference potential. 
     
     
       14. The circuit of  claim 13 , wherein programmable links are arranged across the terminals of a number of the plurality of short channel PMOS FETs. 
     
     
       15. The circuit of  claim 10 , wherein the current source comprises a sixth transistor having a gate connected to the reference potential, a first terminal connected to a second voltage source, and a second terminal connected to the second terminal of the second transistor. 
     
     
       16. The circuit of  claim 15 , wherein the sixth transistor is a long channel p-type metal oxide semiconductor (PMOS) field effect transistor (FET). 
     
     
       17. The circuit of  claim 16 , wherein the long channel PMOS FET comprises a plurality of short channel PMOS FETs connected in series drain-to-source, each short channel PMOS FET having a gate connected to the reference potential. 
     
     
       18. The circuit of  claim 17 , wherein programmable links are arranged across the terminals of a number of the plurality of short channel PMOS FETs. 
     
     
       19. The circuit of  claim 10 , wherein the fourth transistor has a gate terminal connected to a read control signal that is driven towards a magnitude of the second voltage source during reading of the programmable memory cell. 
     
     
       20. A circuit for reading a programmable memory cell, comprising:
 a first transistor and a second transistor connected in series between a current source and a ground reference, wherein a gate of the second transistor is connected to a first voltage source; 
 a third transistor connected in series between a bias current source and a gate of the first transistor, wherein a gate of the third transistor is connected to a drain of the second transistor; 
 a fourth transistor connected in series between the programmable memory cell and the gate of the first transistor, wherein a gate of the fourth transistor is connected to a read control signal line, 
 wherein the bias current source includes a fifth transistor connected in series between a second voltage source having a greater voltage magnitude than the first voltage source and the third transistor, the fifth transistor having a gate directly connected to the ground reference, and wherein an output terminal of the circuit is connected to a drain of the third transistor.