Method of optimization of a manufacturing process of an integrated circuit layout

Abstract

A computer-implemented method, article of manufacture, and computer system for optimization of a manufacturing process of an integrated circuit or IC layout. The method includes: receiving input; organizing IC patterns; selecting IC patterns amongst the organized IC patterns; and optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns.

What is claimed is: 
     
       1. A computer-implemented method of optimization of a manufacturing process of an integrated circuit or IC layout, the method comprising:
 receiving input; 
 organizing IC patterns; 
 selecting IC patterns amongst the organized IC patterns; and 
 optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns using a computer; 
 wherein the steps of receiving input and organizing IC patterns are performed prior to selecting IC patterns and the step of organizing IC patterns includes a condition to be satisfied of the IC patterns; and 
 wherein the input comprises: 
 a set P of IC patterns S 1 , . . . S P  extracted from the IC layout and a set F of features F 1 , . . . F P , respectively associated to the IC patterns of the set P; and 
 a distance function D(F i , F j ) for evaluating a distance d=D(F i , F j ) between two IC patterns S i , S j , based on respective features F i , F j  thereof, such that a distribution of pairs I 0 (d) can be determined, wherein the pairs I 0 (d) are of IC patterns of the set P with respect to a distance d between the pairs. 
 
     
     
       2. The method according to  claim 1 , wherein the input further comprises:
 a probability distribution function I(d) (PDF) that has one or more parameters such that the PDF matches the distribution I 0 (d) of pairs of IC patterns, 
 wherein at the step of organizing IC patterns, the condition can be satisfied via the one or more parameters of the PDF or a related function. 
 
     
     
       3. The method according to  claim 2 , further comprising:
 obtaining the one or more parameters of the PDF, wherein obtaining is performed prior to receiving the PDF as input. 
 
     
     
       4. The method according to  claim 3 , wherein:
 the step of obtaining the one or more parameters of the PDF comprises fitting the PDF onto I 0 (d), by adjusting the one or more parameters of the PDF. 
 
     
     
       5. The method according to  claim 3 , wherein:
 the PDF received can be analytically defined as a finite sum of one or more Gaussian-type functions g 1 (d)-g n (d). 
 
     
     
       6. The method according to  claim 5 , wherein:
 at the step of organizing IC patterns, the condition includes at least one parameter μ 1  that determines a low end average local perturbation of one of the one or more Gaussian-type functions. 
 
     
     
       7. The method according to  claim 5 , wherein:
 at the step of organizing IC patterns, the condition includes at least two parameters of the one or more Gaussian-type functions. 
 
     
     
       8. The method according to  claim 6 , wherein at the step of organizing IC patterns, the condition further includes a parameter μ 1  that determines the low end average local perturbation of one of the one or more Gaussian-type functions and a parameter σ 1  that controls a corresponding width associated with a graphical curve relating to the Gaussian function. 
     
     
       9. The method according to  claim 2 , wherein:
 the related function is a cumulative distribution function (CDF) that corresponds to the PDF; and 
 at the step of organizing IC patterns, the condition is satisfied by setting the condition according to a chosen value of the CDF. 
 
     
     
       10. The method according to  claim 1 , wherein a low end mean distance of a Gaussian function is determined via an iterative procedure. 
     
     
       11. The method according to  claim 1 , wherein the condition at the step of organizing IC patterns is tuned based on an iterative procedure. 
     
     
       12. The method according to  claim 1 , wherein the input further comprises:
 a set P of IC patterns S 1 , . . . S P  extracted from the IC layout and respective features F 1 , . . . F P , 
 wherein each of the respective features are extracted from the IC layout and preferably have a same vector format; and 
 each of the respective features is mapped onto the set P of IC patterns S 1 , . . . S P , such that the distance function D(F i , F j ) can be evaluated for two IC patterns S i , S j , taking respective features F i , F j  of the two IC patterns as arguments. 
 
     
     
       13. A computer-implemented method of manufacturing an integrated circuit (IC), based on a manufacturing process designed according to the method of  claim 1 . 
     
     
       14. A non-transitory article of manufacture tangibly embodying computer readable instructions which, when implemented, cause a computer to carry out the steps of the method of optimization of a manufacturing process of an integrated circuit or IC layout, the method comprising:
 receiving input; 
 organizing IC patterns; 
 selecting IC patterns amongst the organized IC patterns; and 
 optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns; 
 wherein the steps of receiving input and organizing IC patterns are performed prior to selecting IC patterns and the step of organizing IC patterns includes a condition to be satisfied of the IC patterns; and 
 the input comprises: 
 a set P of IC patterns S 1 , . . . S P  extracted from the IC layout and a set F of features F 1 , . . . F P , respectively associated to the IC patterns of the set P; and 
 a distance function D(F i , F j ) for evaluating a distance d=D(F i , F j ) between two IC patterns S i , S j , based on respective features F i , F j  thereof, such that a distribution of pairs I 0 (d) can be determined, wherein the pairs I 0 (d) are of IC patterns of the set P with respect to a distance d between the pairs. 
 
     
     
       15. A computer system having a processor operatively interconnected to a memory device, a graphical display device, a user input device, and a graphical user interface displayed in the graphical display device, allowing the computer system to implement the method of optimization of a manufacturing process of an integrated circuit or IC layout, the method comprising:
 receiving input; 
 organizing IC patterns; 
 selecting IC patterns amongst the organized IC patterns; and 
 optimizing a design of a manufacturing process of the IC layout based on the selected IC patterns; 
 wherein the steps of receiving input and organizing IC patterns are performed prior to selecting IC patterns and the step of organizing IC patterns includes a condition to be satisfied of the IC patterns; and 
 the input comprises: 
 a set P of IC patterns S 1 , . . . S P  extracted from the IC layout and a set F of features F 1 , . . . F P , respectively associated to the IC patterns of the set P; and 
 a distance function D(F i , F j ) for evaluating a distance d=D(F i , F j ) between two IC patterns S i , S j , based on respective features F i , F j  thereof, such that a distribution of pairs I 0 (d) can be determined, wherein the pairs I 0 (d) are of IC patterns of the set P with respect to a distance d between the pairs.