Amorphous semiconductor layer memory device

Abstract

A memory device includes: first and second electrodes; a semiconductor layer of a first conduction type provided on the first electrode side; a solid electrolyte layer containing movable ions and provided on the second electrode side; and an amorphous semiconductor layer of a second conduction type which is provided between the semiconductor layer and the solid electrolyte layer so as to be in contact with the solid electrolyte layer and, at the time of application of voltage to the first and second electrodes, reversibly changes to the first conduction type.

What is claimed is: 
     
       1. A memory device comprising:
 first and second electrodes; 
 a semiconductor layer of a first conduction type between the first electrode and the second electrode; 
 a solid electrolyte layer containing movable ions between the second electrode and the semiconductor layer; and 
 an amorphous semiconductor layer of a second conduction type between the semiconductor layer and the solid electrolyte layer and in contact with the solid electrolyte layer, at the time of application of voltage to the first and second electrodes, the amorphous semiconductor layer reversibly changing to the first conduction type, 
 wherein,
 trap concentration in the amorphous semiconductor layer is equal to or higher than either donor concentration or acceptor concentration. 
 
 
     
     
       2. The memory device according to  claim 1 , wherein by movement of movable ions between the solid electrolyte layer and the amorphous semiconductor layer at the time of application of voltage to the first and second electrodes, the conduction type of the amorphous semiconductor layer changes. 
     
     
       3. The memory device according to  claim 1 , further comprising an intrinsic semiconductor layer having a thickness of 2 nm or larger provided between the amorphous semiconductor layer and the semiconductor layer. 
     
     
       4. The memory device according to  claim 1 , wherein
 temperature at which the movable ions contained in the solid electrolyte layer become movable is 300K or higher, and 
 concentration of the movable ions in the solid electrolyte layer at 300K is equal to or less than trap concentration of the amorphous semiconductor layer. 
 
     
     
       5. The memory device according to  claim 1 , wherein concentration of impurity atoms in the semiconductor layer is equal to or less than trap concentration of the amorphous semiconductor layer. 
     
     
       6. The memory device according to  claim 1 , further comprising a heat barrier layer provided one or both of a portion between the first electrode and the semiconductor layer and a portion between the second electrode and the solid electrolyte layer. 
     
     
       7. The memory device according to  claim 1 , wherein the amorphous semiconductor layer contains a chalcogen element (S, Se, Te) or an alloy of the chalcogen element. 
     
     
       8. The memory device according to  claim 7 , wherein the amorphous semiconductor layer is made of Ge X Te 100-X  (10≦X≦60). 
     
     
       9. A memory device comprising:
 first and second electrodes; 
 a semiconductor layer of a first conduction type between the first electrode and the second electrode; 
 a solid electrolyte layer containing movable ions between the second electrode and the semiconductor layer; 
 an amorphous semiconductor layer of a second conduction type between the semiconductor layer and the solid electrolyte layer and in contact with the solid electrolyte layer, at the time of application of voltage to the first and second electrodes, the amorphous semiconductor layer reversibly changing to the first conduction type; and 
 an intrinsic semiconductor layer having a thickness of 2 nm or larger provided between the amorphous semiconductor layer and the semiconductor layer. 
 
     
     
       10. A memory device comprising:
 first and second electrodes; 
 a semiconductor layer of a first conduction type between the first electrode and the second electrode; 
 a solid electrolyte layer containing movable ions between the second electrode and the semiconductor layer; and 
 an amorphous semiconductor layer of a second conduction type between the semiconductor layer and the solid electrolyte layer and in contact with the solid electrolyte layer, at the time of application of voltage to the first and second electrodes, the amorphous semiconductor layer reversibly changing to the first conduction type, 
 wherein,
 temperature at which the movable ions contained in the solid electrolyte layer become movable is 300K or higher, and 
 concentration of the movable ions in the solid electrolyte layer at 300K is equal to or less than trap concentration of the amorphous semiconductor layer. 
 
 
     
     
       11. A memory device comprising:
 first and second electrodes; 
 a semiconductor layer of a first conduction type between the first electrode and the second electrode; 
 a solid electrolyte layer containing movable ions between the second electrode and the semiconductor layer; and 
 an amorphous semiconductor layer of a second conduction type between the semiconductor layer and the solid electrolyte layer and in contact with the solid electrolyte layer, at the time of application of voltage to the first and second electrodes, the amorphous semiconductor layer reversibly changing to the first conduction type, 
 wherein,
 concentration of impurity atoms in the semiconductor layer is equal to or less than trap concentration of the amorphous semiconductor layer. 
 
 
     
     
       12. A memory device comprising:
 first and second electrodes; 
 a semiconductor layer of a first conduction type between the first electrode and the second electrode; 
 a solid electrolyte layer containing movable ions between the second electrode and the semiconductor layer; 
 an amorphous semiconductor layer of a second conduction type between the semiconductor layer and the solid electrolyte layer and in contact with the solid electrolyte layer, at the time of application of voltage to the first and second electrodes, the amorphous semiconductor layer reversibly changing to the first conduction type; and 
 a heat barrier layer provided one or both of a portion between the first electrode and the semiconductor layer and a portion between the second electrode and the solid electrolyte layer.