Patch-clamp providing on-chip thermal gradient

Abstract

A patch clamp system providing precise and rapid temperature control of constrained cell membranes employs the thermal element attached to the substrate of the patch clamp. In one embodiment, the thermal element is a Peltier device fabricated on a silicon membrane wafer bonded to the substrate of the patch clamp.

We claim: 
     
       1. A patch clamp chip for electrophysiology comprising:
 a substrate having an outer surface; 
 a hole extending through the substrate and opening at the outer surface to provide a location adapted for immobilization of a cell membrane in an electrically sealing attachment against the opening; and 
 a thermal element fixed to the outer surface proximate to the opening adapted to heat a cell membrane positioned on the opening according to a received electrical signal wherein the thermal element is a Peltier device and, wherein the thermal element is separated from a liquid by an insulating layer. 
 
     
     
       2. The patch clamp chip of  claim 1  wherein the substrate is an insulating material. 
     
     
       3. The patch clamp chip of  claim 2  wherein the substrate is selected from the group consisting of glasses and quartz. 
     
     
       4. The patch clamp chip of  claim 1  wherein the hole is less than 1000 nanometers in diameter. 
     
     
       5. The patch clamp chip of  claim 1  wherein the Peltier device is adapted to cool the cell membrane positioned on the opening according to a received electrical signal. 
     
     
       6. The patch clamp chip of  claim 1  wherein the Peltier device is a semiconducting membrane having n- and p-doped regions. 
     
     
       7. The patch clamp chip of  claim 6  wherein the semiconducting membrane is less than 100 micrometers in thickness. 
     
     
       8. The patch clamp chip of  claim 1  wherein the opening provides an outward flaring crater at the outer surface. 
     
     
       9. The patch clamp chip of  claim 1  wherein the opening has a diameter of less than 20 nm. 
     
     
       10. The patch clamp chip of  claim 8  wherein the opening has a surface finish suitable for establishing a gigaohm seal with a cell membrane. 
     
     
       11. A method of fabricating a patch clamp chip for electrophysiology of a type having a substrate having an outer surface; a hole extending through the substrate and opening at the outer surface to provide a location adapted for immobilization of a cell membrane sealed against the opening; and a thermal element fixed to the outer surface proximate to the opening adapted to heat a cell membrane positioned on the opening according to a received electrical signal; the method comprising the steps of:
 (a) fabricating a silicon membrane having at least one aperture therethrough and having a Peltier device adjacent to the opening integrated into the silicon membrane to provide the thermal element; 
 (b) bonding the silicon membrane to the substrate such that the location for immobilization is centered within the aperture in the silicon membrane; and 
 (c) providing electrical contacts communicating with the Peltier device for an application of the electrical signal to control a temperature in a region of the aperture. 
 
     
     
       12. The method of  claim 11  further including the step of fabricating the silicon membrane on a silicon substrate and then releasing the silicon membrane from the silicon substrate by selective etching. 
     
     
       13. The method of  claim 12  further including the step of bonding the silicon membrane to the substrate before release from the silicon substrate by selective etching. 
     
     
       14. The method of  claim 11  further including the step of fabricating the Peltier device by doping adjacent n- and p-regions and interconnecting them by metallization paths on an exposed surface of the silicon membrane after it has been bonded to the substrate and wherein the electrical contacts are metallization paths on the exposed surface of the silicon membrane. 
     
     
       15. The method of  claim 11  wherein the step of doping adjacent n- and p-regions applies the regions in a pattern circling the aperture. 
     
     
       16. The method of  claim 11  further including the step of forming the hole in the substrate by:
 (a) creating a multi-layered assembly comprising,
 (i) the substrate material; and 
 (ii) an energy absorbing material being adjacent to one of the opposing outer surfaces so as to define an interface between the substrate and energy absorbing materials; 
 
 (b) after creating the multi-layered assembly, applying a laser through the multi-layered assembly so that it passes into and has energy absorbed by the energy absorbing material; and 
 (c) producing a shock wave at the interface to remove material from and create a hole through an entire thickness of the substrate material in a direction of propagation that begins at the interface and extends toward the outer surface of the substrate material that opposes the interface. 
 
     
     
       17. The method of  claim 11  further including the steps of:
 (d) attaching a cell membrane over the opening; 
 (e) performing electrical measurements of the electrical characteristics of the cell membrane while, applying a temperature gradient to the cell membrane through current passed through the Peltier device. 
 
     
     
       18. The method of  claim 17  wherein the temperature gradient heats a region near the cell membrane with respect to a fluid surrounding the cell membrane. 
     
     
       19. The method of  claim 18  wherein the temperature gradient cools a region near the cell membrane with respect to a fluid surrounding the cell membrane.