Schottky junction source/drain transistor and method of making

Abstract

A method of making a transistor, comprising: providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; forming an insulating layer over the semiconductor substrate; forming a depleting layer over the insulating layer; etching the depleting layer and the insulating layer; forming a metal layer over the semiconductor substrate; performing thermal annealing; and removing the metal layer. As advantages of the present invention, an upper outside part of each of the sidewalls include a material that can react with the metal layer, so that metal on two sides of the sidewalls is absorbed during the annealing process, preventing the metal from diffusing toward the semiconductor layer, and ensuring that the formed Schottky junctions can be ultra-thin and uniform, and have controllable and suppressed lateral growth.

We claim: 
     
       1. A method of making a transistor, comprising:
 providing a semiconductor substrate; 
 forming a gate stack over the semiconductor substrate; 
 forming an insulating layer over the semiconductor substrate, the insulating layer further covering the gate stack; 
 forming a depleting layer over the insulating layer; 
 etching the depleting layer and the insulating layer to form composite sidewalls on two sides of the gate stack, an upper outside part of the sidewalls being formed of the depleting layer while a remainder part of the sidewalls being formed of the insulating layer; 
 forming a metal layer over the semiconductor substrate, the metal layer further covering the gate stack and the sidewalls; 
 performing thermal annealing to form source/drain Schottky junctions in the semiconductor substrate on two sides of the gate stack, wherein, during the annealing, metal covering the sidewalls is absorbed by reaction with the depleting layer in the composite sidewalls; and 
 removing the metal layer on the semiconductor substrate and reaction product from metal reacting with the depleting layer in the composite sidewalls. 
 
     
     
       2. The method of  claim 1 , wherein the semiconductor substrate includes single crystal silicon and the metal layer includes nickel. 
     
     
       3. The method of  claim 2 , wherein the depleting layer includes germanium. 
     
     
       4. The method of  claim 2 , wherein removing the metal layer is by chemical etching, using an etchant solution including sulfuric acid and hydrogen peroxide. 
     
     
       5. The method of  claim 1 , wherein the thermal annealing further comprises first and second annealing steps, the first annealing step being performed with annealing temperature ranging from 250 ° C. to 350 ° C. , the second annealing step being performed with annealing temperature ranging from 350 ° C. to 600 ° C. 
     
     
       6. The method of  claim 1 , wherein the depleting layer includes germanium. 
     
     
       7. The method of  claim 1 , wherein the depleting layer in the composite sidewall is separated from the substrate by the insulator layer. 
     
     
       8. A transistor made by:
 forming a gate stack over a semiconductor substrate; 
 forming sidewalls on two sides of the gate stack, each respective sidewall comprising a depleting layer forming an upper outside part of the respective sidewall and an insulating layer forming a remainder part of the respective sidewall; 
 forming a metal layer over the semiconductor substrate, the metal layer further covering the gate stack and the sidewalls; and 
 performing thermal annealing to form source/drain Schottky junctions in the semiconductor substrate on two sides of the gate stack, wherein, during the annealing, the depleting layer reacts with parts of the metal layer covering the sidewalls to prevent metal in the parts of the metal layer from diffusing toward and reacting with the semiconductor substrate. 
 
     
     
       9. The transistor of  claim 8 , wherein forming the sidewalls comprises:
 forming the insulating layer over the semiconductor substrate; 
 forming the depleting layer over the insulating layer; and 
 etching the depleting layer and the insulating layer to form the sidewalls. 
 
     
     
       10. The transistor of  claim 8 , further comprising removing unreacted metal in the metal layer and reaction product from the depleting layer reacting with the parts of the metal layer covering the sidewalls. 
     
     
       11. The transistor of  claim 10 , wherein removing is by chemical etching, using an etchant solution including sulfuric acid and hydrogen peroxide. 
     
     
       12. The transistor of  claim 8 , wherein the semiconductor substrate includes single crystal silicon and the metal layer includes nickel. 
     
     
       13. The transistor of  claim 12 , wherein the depleting layer includes germanium. 
     
     
       14. The transistor of  claim 8 , wherein the thermal annealing further comprises first and second annealing steps, the first annealing step performed with annealing temperature ranging from 250° C. to 350° C. , the second annealing step performed with an annealing temperature ranging from 350° C. to 600° C.