Method of producing and decoding error correction code and apparatus therefor

Abstract

An apparatus and method for producing error correction code and error correction decoding are provided. The method for producing error correction code includes generating an asymmetric matrix by arranging input data bits in a matrix of a predefined size and adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; primarily encoding the asymmetric matrix by adding one or more parity bits to each row; and secondarily encoding the primarily encoded matrix by adding one or more parity bits to each column of the encoded matrix.

What is claimed is: 
     
       1. A method for producing error correction code, the method comprising:
 generating an asymmetric matrix by arranging input data bits in a matrix of a predefined size and adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; 
 primarily encoding the asymmetric matrix by adding one or more parity bits to each row; and 
 secondarily encoding the primarily encoded matrix by adding one or more parity bits to each column of the encoded matrix. 
 
     
     
       2. The method of  claim 1 , wherein the primarily encoding of the asymmetric matrix comprises calculating the one or more parity bits based on data bits of each row of the asymmetric matrix and adding the calculated parity bits to the each row. 
     
     
       3. The method of  claim 1 , wherein the secondary encoding of the primarily encoded matrix comprises calculating the one or more parity bits based on data bits of the primarily encoded matrix and adding the calculated parity bits to the each column of the primarily encoded matrix. 
     
     
       4. The method of  claim 1 , wherein a length of the each row of the primarily encoded matrix is different from a length of the each column of the secondarily encoded matrix and a coding rate varies with the lengths of the each row and the each column. 
     
     
       5. The method of  claim 1 , wherein when the zero bit row is added in the generating of the asymmetric matrix, a coding rate of the primarily and secondarily encoded matrix is a product of a first coding rate and a second coding rate where the first coding rate is obtained by dividing the number of data bits included in a row of the encoded matrix by the number of the entire bits of the row and the second coding rate is obtained by dividing the number of data bits included in a column by a value resulting from subtracting the number of zero bits from the number of the entire bits of the column. 
     
     
       6. The method of  claim 1 , wherein when the zero bit column is added in the generating of the asymmetric matrix, a coding rate of the primarily and secondarily encoded matrix is a product of a first coding rate and a second coding rate where the first coding rate is obtained by dividing the number of data bits included in a row of the encoded matrix by a value resulting from subtracting the number of zero bits from the number of the entire bits of the row and the second coding rate is obtained by dividing the number of data bits included in a column of the encoded matrix by the number of the entire bits of the column. 
     
     
       7. The method of  claim 1 , wherein when the zero bit row and the zero bit column are added in the generating of the asymmetric matrix, a coding rate of the primarily and secondarily encoded matrix is a product of a first coding rate and a second coding rate where the first coding rate is obtained by dividing the number of data bits included in a row of the encoded matrix by a value resulting from subtracting the number of zero bits from the number of the entire bits of the row and the second coding rate is obtained by dividing the number of data bits included in a column of the encoded matrix by a value resulting from subtracting the number of zero bits from the number of the entire bits of the column. 
     
     
       8. The method of  claim 1 , wherein a coding rate of the primarily and secondarily encoded matrix varies with the number of zero bits. 
     
     
       9. The method of  claim 1 , further comprising:
 removing the zero bit column and/or the zero bit row, which have been added for generating the asymmetric matrix, from the primarily and secondarily encoded matrix. 
 
     
     
       10. A method for error correction decoding, the method comprising:
 receiving a data matrix which has been error-correction encoded and adding as many zero bits as the number of zero bits that were added when the data matrix was encoded; 
 checking a parity bit of each column of the data matrix which have the zero bits added thereto in an effort to primarily decode data in the each column; and 
 checking a parity bit of each row of the data matrix which have the zero bits added thereto in an effort to secondarily decode data in the each row. 
 
     
     
       11. The method of  claim 10 , further comprising:
 removing the zero bits which have been added as many as the number of the zero bits that were removed when the data matrix was encoded. 
 
     
     
       12. An apparatus for producing error correction code, the apparatus comprising:
 an asymmetric matrix generator configured to arrange input data bits in a matrix of a predefined size and generate an asymmetric matrix by adding a zero bit column and/or a zero bit row, each of the column and the row consisting of zero bits, to the matrix; 
 a primary encoder configured to encode the asymmetric matrix by adding a parity bit to each row; and 
 a secondary encoder configured to encode the primarily encoded matrix by adding a parity bit to each column of the primarily encoded matrix. 
 
     
     
       13. The apparatus of  claim 12 , further comprising:
 a zero bit remover configured to remove one or more zero bits which have been added to the matrix encoded by the primary encoder and the secondary encoder. 
 
     
     
       14. An apparatus for error correction decoding, the apparatus comprising:
 a zero bit adder configured to receive an error-correction encoded data matrix and add as many zero bits as the number of zero bits that were added when the matrix was encoded; 
 a primary decoder configured to check a parity bit of each column of the matrix which have the zero bits added thereto in an effort to decode data of the each column; and 
 a secondary decoder configured to check a parity bit of each row of the matrix decoded by the primary decoder in an effort to decode data of the each row. 
 
     
     
       15. The apparatus of  claim 14 , further comprising:
 a zero bit remover configured to remove the zero bits which have been added by the zero bit adder from the matrix decoded by the secondary decoder.