Low offset, fast response voltage controlled current source and controlling method thereof

Abstract

The present invention relates to a low offset and fast response voltage controlled current source, controlling method, and a power supply thereof. In one embodiment, a voltage controlled current source can include: a clock signal generator, a first operational amplifier, an input offset eliminator, a sampling and holding circuit, and an output circuit. The input offset eliminator can receive a clock signal, an input voltage, and a feedback voltage, and can (i) store and then eliminate an input offset of the first operation amplifier, and generate an error signal in accordance with an error between the input and feedback voltages when the clock signal is active, and (ii) generate the error signal in accordance with the stored input offset and the error between the input and feedback voltages when the clock signal is inactive.

What is claimed is: 
     
       1. A voltage controlled current source configured to drive an output load based on an input voltage, the voltage controlled current source comprising:
 a) a clock signal generator configured to generate a clock signal based on a square-waveform control signal, wherein said clock signal comprises a square waveform signal with a predetermined duty cycle during an active portion of said control signal, and wherein said clock signal is in an inactive state during an inactive portion of said control signal; 
 b) a first operational amplifier having a first terminal configured to receive said input voltage, and a second terminal configured to receive a feedback voltage of said output load; 
 c) an input offset eliminator configured to receive said clock signal, said input voltage, and said feedback voltage, wherein said input offset eliminator is configured to (i) store and then eliminate an input offset of said first operation amplifier, and to generate an error signal in accordance with an error between said input and feedback voltages when said clock signal is active and to (ii) generate said error signal in accordance with said stored input offset and said error between said input and feedback voltages when said clock signal is inactive; 
 d) a sampling and holding circuit configured to receive an output signal of said first operational amplifier and said control signal, wherein energy is stored in accordance with said output signal of said first operational amplifier during said active portion of said control signal, and wherein said stored energy is maintained by said sampling and holding circuit during said inactive portion of said control signal; and 
 e) an output circuit coupled to said sampling and holding circuit, said output circuit being configured to drive said output load during said active portion of said control signal. 
 
     
     
       2. The voltage controlled current source of  claim 1 , wherein a duty cycle of said control signal is variable, and a duty cycle of said clock signal is fixed. 
     
     
       3. The voltage controlled current source of  claim 1 , wherein said input offset eliminator comprises an automatic zero calibrator and a first offset information storage circuit. 
     
     
       4. The voltage controlled current source of  claim 3 , wherein said automatic zero calibrator comprises a first switch, a second switch, a third switch, a fourth switch, a second operational amplifier, and a second input offset information storage circuit, wherein:
 a) said first switch is coupled between an inverting input terminal of said first operational amplifier and an inverting input terminal of said second operational amplifier; 
 b) said second switch is coupled between said non-inverting input terminal of said first operational amplifier and said inverting input terminal of said second operational amplifier; 
 c) said third switch is coupled between an output of said second operational amplifier and said second input offset information storage circuit; 
 d) said fourth switch is coupled between said output of said second operational amplifier and said first input offset information storage circuit; 
 e) when said clock signal is active, said first switch and said fourth switch are on, and said second switch and said third switch are off, and said input offset of said first operational amplifier is eliminated by said automatic zero calibrator; and 
 f) when said clock signal is inactive, said first switch and said fourth switch are off, and said second switch and said third switch are on, and said input offset of said second operational amplifier is eliminated by said automatic zero calibrator. 
 
     
     
       5. The voltage controlled current source of  claim 4 , wherein said first input offset information storage circuit comprises a first capacitor coupled between said first operational amplifier and ground, and wherein said second input offset information storage circuit comprises a second capacitor coupled between said second operational amplifier and ground. 
     
     
       6. The voltage controlled current source of  claim 1 , wherein said sampling and holding circuit comprises a first switch group, a second switch group, a third capacitor, and an enhancing driving circuit, wherein:
 a) said first switch group comprises a fifth switch and a sixth switch coupled in series between said output of said first operational amplifier and said enhancing driving circuit; 
 b) said enhancing driving circuit is coupled to said output circuit to enhance a response speed; 
 c) said third capacitor is coupled between ground and a common node of said fifth and sixth switches; and 
 d) said second switch group comprises a seventh switch and an eighth switch, said seventh switch being coupled between ground and a common node of said sixth switch and said enhancing driving circuit, said eighth switch being coupled between said enhancing driving circuit and ground. 
 
     
     
       7. The voltage controlled current source of  claim 6 , wherein there is a dead time between switching sequences of said first switch group and said second switch group. 
     
     
       8. The voltage controlled current source of  claim 7 , wherein said enhancing driving circuit further comprises a source follower having a first power switch and a second power switch, a push-pull circuit having a third power switch and a fourth power switch, and a ninth switch. 
     
     
       9. The voltage controlled current source of  claim 1 , wherein said output circuit comprises a power switch which coupled between said output load and ground through an output resistor, and wherein a voltage at a common node of said power switch and said output resistor is configured as said feedback voltage of said output load. 
     
     
       10. The voltage controlled current source of  claim 1 , further comprising an input voltage generator having an input current source and an input resistor coupled in series to ground, wherein a voltage at a common node of said input current source and said input resistor is configured as said input voltage. 
     
     
       11. A power supply, comprising:
 a) said voltage controlled current source of  claim 1 ; 
 b) a power stage circuit configured to receive an input signal and a pulse-width modulation (PWM) control signal, and to generate an output voltage coupled to said voltage controlled current source; and 
 c) a controlling circuit configured to generate said PWM control signal in accordance with said feedback signal of said output load, 
 d) wherein said voltage controlled current source is configured to receive said PWM control signal, to eliminate said input offset and to generate an output current according to said input voltage and said feedback signal of said output load to drive said output load. 
 
     
     
       12. A controlling method for a voltage controlled current source configured to drive an output load in accordance with an input voltage, the method comprising:
 a) receiving a square-waveform control signal; 
 b) generating a clock signal based on said control signal, wherein said clock signal comprises a square waveform signal with a predetermined duty cycle during an active portion of said control signal, and wherein said clock signal is in an inactive state during an inactive portion of said control signal; 
 c) when said clock signal is active, storing input offset information and eliminating an input offset of a first operational amplifier by using said input voltage and a feedback voltage of said output load, and generating an error signal according to an error between said input and feedback voltages; 
 d) when said clock time is inactive, generating said error signal according to said error between said input and feedback voltages, and storing said input offset information; 
 e) storing energy in accordance an output signal of said first operational amplifier during said active portion of said control signal; 
 f) maintaining said stored energy during said inactive portion of said control signal; 
 g) driving said output load in accordance with said stored energy at an initial active moment of said control signal; and 
 h) driving said output load in accordance with said output signal during said active portion of said control signal. 
 
     
     
       13. The method of  claim 12 , wherein a duty cycle of said control signal is variable, and a duty cycle of said clock signal is fixed. 
     
     
       14. The method of  claim 12 , further comprising:
 a) eliminating, when said clock signal is active, said input offset of said first operational amplifier by using a second operational amplifier in accordance with said input voltage and said feedback voltage of said output load; and 
 b) storing and then eliminating said input offset of said first operational amplifier when said clock signal is inactive. 
 
     
     
       15. The method of  claim 12 , further comprising enhancing said output signal of said first operational amplifier.