Configurable memory controller/memory module communication system

Abstract

A memory system includes a first memory module and a second memory module. A memory controller is coupled to the first and second memory modules and reads configuration information from the first and second memory modules using a memory channel. The controller also configures a switch coupled between the controller and one of the memory modules to communicate using either a chip select line or a memory address line.

What is claimed is: 
     
       1. A memory system comprising:
 a first memory module; 
 a second memory module; 
 at least one switch coupled to at least one of the first memory module and the second memory module; and 
 a memory controller coupled to each of the first memory module and the second memory module, wherein the memory controller is coupled to at least one of the first memory module and the second memory module through the least one switch via a plurality of signal lines, and wherein the memory controller is operable to determine a memory module type for at least one of the first memory module and the second memory module, and configure the at least one switch based on at least one memory module type requirement and the signaling needs of at least one of the first memory module and the second memory module to allow communication between the memory controller and at least one of the first memory module and the second memory module using at least one of the plurality of signals lines. 
 
     
     
       2. The memory system of  claim 1 , wherein at least one of the first memory module and the second memory modules includes a dual in-line memory module (DIMM). 
     
     
       3. The memory system of  claim 2 , wherein at least one of the first memory module and the second memory module includes an unbuffered DIMM (UDIMM), a registered DIMM (RDIMM), or a load reduced DIMM (LR-DIMM). 
     
     
       4. The memory system of  claim 1 , wherein the memory module is operable to determine the memory module type for at least one of the first memory module and the second memory module using serial presence detect (SPD) information. 
     
     
       5. The memory system of  claim 1 , wherein at least one of the first memory module and the second memory module includes a single rank, dual rank, quad rank, or octal rank. 
     
     
       6. The memory system of  claim 1 , wherein the plurality of signal lines include at least one of a data signal line, an address signal line, and a control signal line. 
     
     
       7. The memory system of  claim 6 , wherein the control signal line includes a chip select signal line. 
     
     
       8. An information handling system (IHS) comprising:
 a processor; and 
 a memory system coupled to the processor, wherein the memory system includes:
 a first memory module; 
 a memory controller; and 
 a switch coupling the first memory module to the memory controller via a plurality of signal lines; 
 wherein the memory controller is operable determine a memory module type for the first memory module and configure the switch based on at least one memory module type requirement and the signaling needs of the first memory module to allow communication between the memory controller and the first memory module using at least one of the plurality of signal lines. 
 
 
     
     
       9. The IHS of  claim 8 , wherein the first memory module includes a dual in-line memory module (DIMM). 
     
     
       10. The IHS of  claim 8 , wherein the first memory module includes an unbuffered DIMM (UDIMM), a registered DIMM (RDIMM), or a load reduced DIMM (LR-DIMM). 
     
     
       11. The IHS of  claim 8 , wherein the memory controller is operable determine the memory module type of the first memory module using serial presence detect (SPD) information. 
     
     
       12. The IHS of  claim 8 , wherein the first memory module includes a single rank, dual rank, quad rank, or octal rank. 
     
     
       13. The IHS of  claim 8 , wherein the plurality of signal lines include at least one of a data signal line, an address signal line, and a control signal line. 
     
     
       14. The IHS of  claim 13  wherein the control signal line includes a chip select signal line. 
     
     
       15. A method comprising:
 providing a memory controller coupled to a first memory module, wherein at least one switch is coupled between the memory controller and the first memory module by a plurality of signal lines; 
 determining a memory module type for the first memory module; and 
 configuring the at least one switch based on at least one memory module type requirement and the signaling needs of the first memory module to allow communication between the memory controller and the first memory module using at least one of the plurality of signaling lines. 
 
     
     
       16. The method of  claim 15 , wherein the first memory module includes a dual in-line memory module (DIMM). 
     
     
       17. The method of  claim 15 , wherein the first memory module includes an unbuffered DIMM (UDIMM), a registered DIMM (RDIMM), or a load reduced DIMM (LR-DIMM). 
     
     
       18. The method of  claim 15 , wherein the determining the memory module type of the first memory module is performed using serial presence detect (SPD) information. 
     
     
       19. The method of  claim 15 , wherein the first memory module includes a single rank, dual rank, quad rank, or octal rank. 
     
     
       20. The method of  claim 15 , wherein the plurality of signal lines include at least one of a data signal line, an address signal line, and a control signal line.