P
US8713348B2ActiveUtilityPatentIndex 40

Apparatus for performing timer management regarding a system timer scheduler service, and associated method

Assignee: CHEN MING-CHIPriority: Aug 30, 2010Filed: Aug 30, 2010Granted: Apr 29, 2014
Est. expiryAug 30, 2030(~4.2 yrs left)· nominal 20-yr term from priority
Inventors:CHEN MING CHIYANG CHING-CHAOCHAN CHUN-KUN
G06F 1/329Y02D10/00G06F 1/3206G06F 1/14G06F 9/4825
40
PatentIndex Score
1
Cited by
17
References
20
Claims

Abstract

An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service. An associated method for performing timer management regarding a system timer scheduler service is also provided, and can be applied to the apparatus. In particular, the apparatus and the method can give considerations to both run-time power consumption and sleep mode power consumption. For example, the hardware-based OS timer can support an event-based OS timer scheduler to save the run-time power consumption. In another example, the hardware-based OS timer can support timer alignment in accordance with modulator/demodulator (modem) activities to minimize the sleep mode power consumption.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An apparatus for performing timer management regarding a system timer scheduler service, comprising:
 a processor arranged to control operations of the apparatus; 
 an ordinary timer arranged to provide the processor with time ticks, for use of timing control; and 
 a hardware-based Operating System (OS) timer arranged to provide the processor with at least one scheduler timer, for use of the system timer scheduler service, wherein the hardware-based OS timer comprises two counters for counting an alignment frame number (AFN) and an un-alignment frame number (UFN), respectively. 
 
     
     
       2. The apparatus of  claim 1 , wherein with aid of the hardware-based OS timer, the system timer scheduler service provides an event-based OS timer scheduler. 
     
     
       3. The apparatus of  claim 2 , wherein with the aid of the hardware-based OS timer, the system timer scheduler service provides the event-based OS timer scheduler to save run-time power consumption. 
     
     
       4. The apparatus of  claim 1 , wherein with aid of the hardware-based OS timer, the system timer scheduler service provides timer alignment in accordance with modulator/demodulator (modem) activities; and whether the modem activities are inactive depends on whether the ordinary timer is in a sleep mode. 
     
     
       5. The apparatus of  claim 4 , wherein with the aid of the hardware-based OS timer, the system timer scheduler service provides timer alignment in accordance with the modulator/demodulator (modem) activities to minimize sleep mode power consumption. 
     
     
       6. The apparatus of  claim 1 , wherein the AFN is utilized for controlling an expiration time of a target event that is delayable in a sleep mode, and the UFN is utilized for controlling an expiration time of a target event that is non-delayable in any mode. 
     
     
       7. The apparatus of  claim 1 , wherein the two counters are count-down timers; and the UFN is non-negative, and there is no limitation for the AFN to temporarily reach a negative value. 
     
     
       8. The apparatus of  claim 1 , wherein a duration of a tick frame of the hardware-based OS timer is the same as that of a tick frame of the ordinary timer. 
     
     
       9. The apparatus of  claim 8 , wherein when the ordinary timer enters a sleep mode, the hardware-based OS timer enters the sleep mode accordingly, causing a whole chip of the apparatus to fall asleep. 
     
     
       10. The apparatus of  claim 9 , wherein when the ordinary timer enters the sleep mode, the hardware-based OS timer enters the sleep mode at a same time. 
     
     
       11. A method for performing timer management regarding a system timer scheduler service, the method being applied to an apparatus, the apparatus comprising a processor arranged to control operations of the apparatus, the method comprising:
 utilizing an ordinary timer to provide the processor with time ticks, for use of timing control; and 
 utilizing a hardware-based Operating System (OS) timer to provide the processor with at least one scheduler timer, for use of the system timer scheduler service, wherein the hardware-based OS timer comprises two counters for counting an alignment frame number (AFN) and an un-alignment frame number (UFN), respectively. 
 
     
     
       12. The method of  claim 11 , wherein with aid of the hardware-based OS timer, the system timer scheduler service provides an event-based OS timer scheduler. 
     
     
       13. The method of  claim 12 , wherein with the aid of the hardware-based OS timer, the system timer scheduler service provides the event-based OS timer scheduler to save run-time power consumption. 
     
     
       14. The method of  claim 11 , wherein with aid of the hardware-based OS timer, the system timer scheduler service provides timer alignment in accordance with modulator/demodulator (modem) activities; and whether the modem activities are inactive depends on whether the ordinary timer is in a sleep mode. 
     
     
       15. The method of  claim 14 , wherein with the aid of the hardware-based OS timer, the system timer scheduler service provides timer alignment in accordance with the modulator/demodulator (modem) activities to minimize sleep mode power consumption. 
     
     
       16. The method of  claim 11 , wherein the step of utilizing the hardware-based OS timer to provide the processor with the at least one scheduler timer further comprises:
 utilizing the AFN to control an expiration time of a target event that is delayable in a sleep mode; and 
 utilizing the UFN to control an expiration time of a target event that is non-delayable in any mode. 
 
     
     
       17. The method of  claim 11 , wherein the two counters are count-down timers; and the UFN is non-negative, and there is no limitation for the AFN to temporarily reach a negative value. 
     
     
       18. The method of  claim 11 , wherein a duration of a tick frame of the hardware-based OS timer is the same as that of a tick frame of the ordinary timer. 
     
     
       19. The method of  claim 18 , further comprising:
 when the ordinary timer enters a sleep mode, controlling the hardware-based OS timer to enter the sleep mode accordingly, causing a whole chip of the apparatus to fall asleep. 
 
     
     
       20. The method of  claim 19 , wherein the step of controlling the hardware-based OS timer to enter the sleep mode accordingly further comprises:
 when the ordinary timer enters the sleep mode, controlling the hardware-based OS timer to enter the sleep mode at a same time.

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