Variable resistance memory

Abstract

A variable resistance memory according to an embodiment includes: a first wiring; a second wiring intersecting with the first wiring; a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; a second electrode connected to the second wiring, the second electrode facing to the first electrode; a variable resistance layer provided between the first electrode and the second electrode; and one of a first insulating layer and a first semiconductor layer formed at side portions of the second electrode. The one of the first insulating layer and the first semiconductor layer, and the second electrode form voids at the side portions of the second electrode.

What is claimed is: 
     
       1. A variable resistance memory comprising:
 a first wiring; 
 a second wiring intersecting with the first wiring; 
 a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; 
 a second electrode connected to the second wiring, the second electrode facing to the first electrode; 
 a variable resistance layer provided between the first electrode and the second electrode; and 
 a first semiconductor layer formed at side portions of the second electrode, the first semiconductor layer and the second electrode forming voids at the side portions of the second electrode. 
 
     
     
       2. The variable resistance memory according to  claim 1 , further comprising
 a second semiconductor layer containing an impurity, the second semiconductor layer being located between the variable resistance layer and the second electrode. 
 
     
     
       3. The variable resistance memory according to  claim 1 , further comprising
 a first insulating layer located between the variable resistance layer and the second electrode. 
 
     
     
       4. The variable resistance memory according to  claim 1 , wherein the second electrode is a metal-semiconductor compound. 
     
     
       5. The variable resistance memory according to  claim 4 , wherein the second electrode is a silicide, germanide, or germanosilicide of one of Ti, Co, Ni, Pt, W, and Mo. 
     
     
       6. The variable resistance memory according to  claim 5 , wherein the second wiring is made of W. 
     
     
       7. The variable resistance memory according to  claim 1 , wherein the first electrode contains a metal, the metal being ionizable in the variable resistance layer. 
     
     
       8. The variable resistance memory according to  claim 7 , wherein the first electrode is one of Ag, Cu, Au, Al, W, Ti, and Co. 
     
     
       9. The variable resistance memory according to  claim 1 , wherein the variable resistance layer is an amorphous semiconductor. 
     
     
       10. A variable resistance memory comprising:
 a first wiring; 
 a second wiring intersecting with the first wiring; 
 a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; 
 a second electrode connected to the second wiring, the second electrode facing to the first electrode; and 
 a variable resistance layer provided between the first electrode and the second electrode, and provided at side portions of the second electrode, the variable resistance layer being made of a semiconductor, the variable resistance layer and the second electrode forming voids at the side portions of the second electrode. 
 
     
     
       11. The variable resistance memory according to  claim 10 , wherein the second electrode is a metal-semiconductor compound and the variable resistance layer contains at least one element of Si, Ge, and C. 
     
     
       12. The variable resistance memory according to  claim 11 , wherein the second electrode is a silicide, germanide, or germanosilicide of one of Ti, Co, Ni, Pt, W, and Mo. 
     
     
       13. The variable resistance memory according to  claim 12 , wherein the second wiring is made of W. 
     
     
       14. The variable resistance memory according to  claim 10 , wherein the first electrode contains a metal, the metal being ionizable in the variable resistance layer. 
     
     
       15. The variable resistance memory according to  claim 10 , wherein the variable resistance layer is an amorphous semiconductor. 
     
     
       16. A variable resistance memory comprising:
 a first wiring; 
 a second wiring intersecting with the first wiring; 
 a first electrode provided in an intersection region between the first wiring and the second wiring, the first electrode being connected to the first wiring; 
 a second electrode connected to the second wiring, the second electrode facing to the first electrode; 
 a variable resistance layer provided between the first electrode and the second electrode; and 
 a first insulating layer provided at side portions of the second electrode, the first insulating layer and the second electrode forming voids at the side portions of the second electrode, 
 wherein a size of each of the voids becomes larger toward the variable resistance layer.