Nonvolatile memory device and program verify method thereof

Abstract

A program verify method of the nonvolatile memory device includes supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array, sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal, supplying a second program verify voltage higher than the first program verify voltage to the word line, and sensing a voltage of the bit line in response to a second sense signal having a lower voltage level than the first sense signal.

What is claimed is: 
     
       1. A program verify method of a nonvolatile memory device, comprising:
 supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array; 
 sensing a voltage of a bit line coupled to the memory cells in response to a first sense signal; 
 supplying a second program verify voltage higher than the first program verify voltage to the word line; and 
 sensing a voltage of the bit line in response to a second sense signal having a lower voltage level than the first sense signal. 
 
     
     
       2. The method of  claim 1 , further comprising:
 supplying a third program verify voltage higher than the second program verify voltage to the word line; and 
 sensing a voltage of the bit line in response to a third sense signal having a lower voltage level than the second sense signal. 
 
     
     
       3. The method of  claim 1 , wherein sensing the voltage of the bit line is performed by coupling the bit line and a sense node of a page buffer in response to the first sense signal or the second sense signal. 
     
     
       4. The method of  claim 1 , further comprising precharging the bit line to a high level before supplying the first sense signal. 
     
     
       5. The method of  claim 4 , further comprising supplying the second sense signal without precharging the bit line. 
     
     
       6. The method of  claim 1 , further comprising supplying the second sense signal voltage with at least two voltage levels. 
     
     
       7. The method of  claim 1 , further comprising supplying the second program verify voltage for a shorter interval than the first program verify voltage. 
     
     
       8. A program verify method of a nonvolatile memory device, comprising:
 supplying a first program verify voltage to a word line coupled to memory cells of a memory cell array; 
 evaluating a voltage of a bit line coupled to the memory cells according to threshold voltages of the memory cells during a first interval; 
 sensing the voltage of the bit line coupled to the memory cells in response to a first sense signal; 
 supplying a second program verify voltage higher than the first program verify voltage to the word line; 
 evaluating a voltage of the bit line according to threshold voltages of the memory cells during a second interval shorter than the first interval; and 
 sensing the voltage of the bit line coupled to the memory cells in response to a second sense signal. 
 
     
     
       9. The method of  claim 8 , wherein the second interval is controlled by adjusting a time at which the second sense signal is enabled. 
     
     
       10. The method of  claim 8 , wherein the second sense signal has a lower voltage level than the first sense signal. 
     
     
       11. The method of  claim 8 , wherein the bit line is precharged before sensing the voltage of the bit line in response to the first signal, and the bit line is not precharged before sensing the voltage of the bit line in response to the second signal. 
     
     
       12. A nonvolatile memory device, comprising:
 a memory cell array configured to include a plurality of memory cells; 
 a voltage supply unit configured to supply operating voltages to a word line of the memory cell array; 
 a page buffer unit coupled to the plurality of memory cells through a bit line; and 
 a controller configured to control operations of the page buffer unit and the voltage supply unit, 
 wherein the controller performs control so that the voltage supply unit sequentially outputs a plurality of program verify voltages to the memory cell array when program verify operations are performed and generates a bit line sense signal so that the page buffer unit senses a voltage of the bit line, and 
 the bit line sense signal is generated having a gradually lower voltage level whenever the program verify voltages are changed. 
 
     
     
       13. The nonvolatile memory device of  claim 12 , wherein the controller controls durations of intervals where the bit line is evaluated by controlling times at which the bit line sense signals are enabled whenever the program verify voltages are changed. 
     
     
       14. The nonvolatile memory device of  claim 13 , wherein each interval comprising the durations of intervals decreases for each subsequent change in the program verify voltage.