Apparatus and method for controlling memory overrun

Abstract

A memory address filter is configurable to emulate memory overrun performance of a legacy memory using an electronic memory of equal or greater capacity. The address filter includes a comparator configured to determine whether a target address is greater than a maximum legacy-address. Memory emulation at target address values greater than the maximum legacy-address value includes one or more of inhibiting the memory transaction; accomplishing the requested memory transaction at the maximum legacy-address value; and accomplishing the requested memory transaction at an address equivalent to the target address wrapped according to the maximum legacy-address value. In some embodiments, the address filter accepts one or more configuration parameters, such as memory depth, wrap-around, and overwrite enable.

What is claimed is: 
     
       1. A method for transacting data with an addressable memory, comprising:
 receiving a target address value of a requested memory transaction; 
 determining whether the target address value is greater than a maximum legacy address value; 
 in response to a determination that the target address value is greater than the maximum legacy address value, emulating a legacy-memory transaction by performing an emulation of a selectable type, wherein the emulation of the selectable type is selectable from between: (a) inhibiting the requested memory transaction; and (b) allowing the requested memory transaction at the maximum legacy address value; and 
 in response to a determination that the target address value is not greater than the maximum legacy address value, executing a standard memory transaction. 
 
     
     
       2. The method of  claim 1 , wherein the emulation of the selectable type comprises inhibiting the requested memory transaction. 
     
     
       3. The method of  claim 1 , wherein the emulation of the selectable type comprises allowing the requested memory transaction at the maximum legacy address value. 
     
     
       4. The method of  claim 1 , wherein the requested memory transaction comprises reading data from the addressable memory. 
     
     
       5. The method of  claim 1 , wherein the requested memory transaction comprises writing data to the addressable memory. 
     
     
       6. The method of  claim 1 , wherein the maximum legacy address value is selectable. 
     
     
       7. A memory-address filter, comprising:
 an input adapted to receive a target address value of a requested memory transaction; 
 an output in communication with an addressable memory; and 
 a legacy-memory emulator in communication with the input and the output, the legacy-memory emulator configured to:
 emulate a legacy memory transaction in response to the target address value being greater than a maximum legacy address value, and 
 perform a standard memory transaction if the target address value is not greater than the maximum legacy address value 
 
 wherein the legacy-memory emulator comprises a mode-selector, and wherein the legacy memory transaction is of a type selectable, using the mode-selector, between: (a) inhibiting the requested memory transaction; and (b) allowing the requested memory transaction at the maximum legacy address value. 
 
     
     
       8. The memory-address filter of  claim 7 , wherein the legacy-memory emulator comprises a comparator circuit determining whether the target address value is greater than the maximum legacy address value. 
     
     
       9. The memory-address filter of  claim 7 , further comprising a storage element configured to store the maximum legacy address value. 
     
     
       10. The memory-address filter of  claim 7 , wherein the mode selector comprises at least one mode selection register storing at least one of a STOP value and a memory overrun enable value. 
     
     
       11. The memory-address filter of  claim 7 , wherein the legacy memory emulator comprises a strobe inhibitor, configured to inhibit a requested write memory transaction in response to the received target address value being greater than the maximum legacy address value. 
     
     
       12. A memory-address filter, comprising:
 means for receiving a target address value of a requested memory transaction; 
 means for determining whether the target address value is greater than a maximum legacy address value; 
 means for, in response to a determination that the target address value is greater than the maximum legacy address value, performing a legacy memory transaction of a type selectable between: (a) inhibiting the requested memory transaction; and (b) allowing the requested memory transaction at the maximum legacy address value; and 
 means for providing the target address value to an addressable memory, in response to a determination that the target address value is not greater than the maximum legacy address value. 
 
     
     
       13. A system comprising:
 automatic test equipment configured to couple to a device under test (DUT) and to execute a test program to perform a test of the DUT, the automatic test equipment comprising the memory-address filter of  claim 7 . 
 
     
     
       14. An automatic test system, comprising:
 automatic test equipment (ATE) configured to couple to a device under test (DUT) and to execute a test program to perform a test of the DUT, the ATE comprising: 
 an input adapted to receive a target ATE memory address value of a requested ATE memory transaction, the target ATE memory address value identifying a target ATE memory address value of an addressable memory of the ATE; 
 an output in communication with the, addressable memory; and 
 a legacy-memory emulator in communication with the input of the ATE and the output of the ATE, the legacy-memory emulator configured to:
 emulate a legacy ATE memory transaction in response to the target ATE memory address value being greater than a maximum ATE legacy address value, and 
 perform a standard ATE memory transaction if the target ATE memory address value of the memory of the ATE is not greater than the maximum ATE legacy address value, 
 
 wherein the legacy-memory emulator comprises a mode-selector, and wherein the legacy ATE memory transaction is of a type selectable, using the mode-selector, from among a plurality of types of legacy ATE memory transactions. 
 
     
     
       15. The automatic test system of  claim 14 , wherein the legacy ATE memory transaction is of a type selectable between: (a) inhibiting the requested ATE memory transaction; (b) allowing the requested ATE memory transaction at the maximum ATE legacy address value; and (c) allowing the requested ATE memory transaction at an overrun-adjusted ATE address value determined by a wrapping of the target ATE address value with respect to the maximum ATE legacy address value. 
     
     
       16. The automatic test system of  claim 15 , wherein the legacy ATE memory transaction is of a type selectable between: (a) inhibiting the requested ATE memory transaction; and (b) allowing the requested ATE memory transaction at the maximum ATE legacy address value.