Fast open circuit detection for open power and ground pins

Abstract

A system and method for identifying opens among parallel connections on a circuit assembly such as a printed circuit board (PCB). In a learn phase performed on a known good circuit assembly, a group of parallel connected pins are excited with a first signal. A second signal, out-of-phase with the first signal, is applied to a second group of pins associated with the component. The amplitude and/or the phase of the second signal and the number and/or specific pins in the second group of pins are selected so that first and second signals coupled to a detector plate proximal to the component substantially offset. During a manufacturing test, signals of comparable amplitude and phase are applied to like pins on a like component of a circuit assembly under test. If the response signal coupled to a like detector plate is below a threshold, it is determined that each pin in the group of parallel connected pins is connected. If the amplitude of the response is over the threshold, one or more of the parallel pins is determined to be open. Additional tests may be performed to identify which of the parallel pins is likely open.

What is claimed is: 
     
       1. A method of testing a circuit assembly comprising a component with a plurality of pins, the method comprising:
 applying a first signal to a first group of the plurality of pins; 
 concurrently with applying the first signal, applying a second signal to a second group of the plurality of pins, the second signal being out of phase with the first signal; 
 with a probe positioned adjacent the component, sensing a response signal, the response signal being in response to the first signal and the second signal as capacitively coupled to the probe from the first group and the second group, respectively; and 
 indicating a test result based on a level of the response signal. 
 
     
     
       2. The method of  claim 1 , wherein the second signal is out of phase with the first signal by half a cycle. 
     
     
       3. The method of  claim 1 , wherein the component comprises a connector. 
     
     
       4. The method of  claim 1 , wherein the first group of the plurality of pins are electrically connected together in the circuit assembly. 
     
     
       5. The method of  claim 4 , wherein the first group of the plurality of pins is a group of power pins. 
     
     
       6. The method of  claim 4 , wherein the first group of the plurality of pins is a group of ground pins. 
     
     
       7. The method of  claim 1 , wherein the second group of the plurality of pins is a group of signal pins. 
     
     
       8. The method of  claim 7 , wherein the group of signal pins are electrically separate with respect to each other within the circuit assembly. 
     
     
       9. The method of  claim 1 , wherein indicating a test result comprises indicating at least one of the pins in the first group is not electrically connected to a trace on a substrate of the circuit assembly. 
     
     
       10. The method of  claim 1 , wherein the probe comprises a plate. 
     
     
       11. The method of  claim 10 , wherein the plate is operably connected to an amplifier. 
     
     
       12. The method of  claim 1 , wherein the first signal oscillates at a frequency in the range of 5-20 KHz. 
     
     
       13. The method of  claim 1 , wherein the first signal is an analog sinusoidal signal. 
     
     
       14. The method of  claim 13 , wherein an amplitude of the first signal is less than an amplitude of a voltage to turn on a semiconductor device in the component. 
     
     
       15. The method of  claim 1 , wherein the first signal is a digital signal. 
     
     
       16. The method of  claim 1 , wherein the component comprises a socket. 
     
     
       17. A method of manufacturing circuit assemblies, the method comprising:
 testing circuit assemblies in accordance with the method of  claim 1 , the circuit assemblies being tested after a first portion of a manufacturing process has been performed; and
 for each circuit assembly tested, selecting steps in a second portion of the manufacturing process based on the indicated test result. 
 
 
     
     
       18. A method of testing a circuit assembly comprising a component with a plurality of pins, the method comprising:
 during a learn phase:
 determining a first group and a second group of the plurality of pins such that when a signal is applied to each of the pins in the first group and a signal of a complementary phase is applied to each of the pins in the second group, the signals coupled from the first group and the second group to a probe adjacent the component have a predetermined value; and 
 
 during a test phase:
 applying a first signal to the first group of the plurality of pins; 
 concurrently with applying the first signal, applying a second signal to the second group of the plurality of pins, the second signal being out of phase with the first signal; 
 with a probe positioned adjacent the component, sensing a response signal, the response signal being representative of a combined level of the first signal and the second signal coupled from the first group and the second group, respectively; and 
 indicating a test result based on the level of the response signal relative to the predetermined value. 
 
 
     
     
       19. The method of  claim 18 , wherein the second signal is out of phase with the first signal by half a cycle. 
     
     
       20. The method of  claim 18 , further comprising, during the learn phase, identifying a threshold, the threshold representative of a change in the response signal from the predetermined value when the second group is reduced by one or more pins, and
 wherein indicating the test result comprises comparing a difference between the response signal and the predetermined value to the threshold. 
 
     
     
       21. The method of  claim 20 , wherein identifying the threshold comprises:
 disconnecting the second signal from a successive pin in the second group; and 
 measuring the response signal when each successive pin is disconnected. 
 
     
     
       22. The method of  claim 18 , further comprising storing a test plan for the circuit assembly, the test plan comprising first and second groups for each of a plurality of components on the circuit assembly. 
     
     
       23. The method of  claim 18 , wherein indicating comprises producing a human perceptible output. 
     
     
       24. The method of  claim 18 , wherein indicating comprises storing a result on a computer storage medium. 
     
     
       25. The method of  claim 18 , wherein when the test result indicates a pin in the first group is open, the method further comprises:
 a location phase, the location phase comprising: 
 for a selected pin in the first group, applying a test signal to a pin in the second group that is adjacent the selected pin; 
 with the probe positioned adjacent the component, measuring a level of the test signal coupled from the pin to the probe; and 
 indicating that the selected pin in the first group is open when the level of the test signal coupled from the component to the probe is above a threshold. 
 
     
     
       26. The method of  claim 25 , wherein the location phase comprises iteratively repeating the acts of applying a test signal and measuring a level of the test signal coupled to the probe with a different one of the plurality of pins in the first group as the selected pin in each iteration until a selected pin is identified for which the level of the test signal coupled from the component to the probe is above the threshold. 
     
     
       27. The method of  claim 18 , wherein during the learn phase, identifying the second group of the plurality of pins comprises connecting, sequentially, signal pins to the second signal to achieve a response signal below a threshold, and adjusting a level of the first signal or the second signal to reduce the response signal, the reduced response signal defining the predetermined value. 
     
     
       28. A computer storage device comprising computer executable instructions that, when executed on a test system having a computer, control the test system to test a circuit assembly comprising a component with a plurality of pins according to a method comprising:
 applying a first signal to a first group of the plurality of pins; 
 concurrently with applying the first signal, applying a second signal to a second group of the plurality of pins, the second signal being out of phase with the first signal; 
 
       with a probe positioned adjacent the component, sensing a response signal, the response signal being in response to the first signal and the second signal as capacitively coupled to the probe from the first group and the second group, respectively; and
 indicating a test result based on a level of the response signal.