P
US8773122B2ActiveUtilityPatentIndex 33

Hall element control circuit

Assignee: KURA TAKESHIPriority: Jun 3, 2010Filed: Jun 3, 2011Granted: Jul 8, 2014
Est. expiryJun 3, 2030(~3.9 yrs left)· nominal 20-yr term from priority
Inventors:KURA TAKESHITSUDA HIROYUKIKAMIYA TOMONORINAGAI HIROKI
G01R 33/0023G01R 33/072G05F 3/02
33
PatentIndex Score
0
Cited by
7
References
3
Claims

Abstract

A first terminal supplies the bias voltage to a high-potential-side input terminal of a hall element. A second terminal supplies the ground potential to a low-potential-side input terminal of the hall element. A P-channel type transistor is configured such that the source terminal is connected to the power supply potential and the drain terminal is connected to the first terminal. An operational amplifier differentially amplifies the voltage between a predetermined set voltage and the voltage at the first terminal so as to control the gate voltage of the P-channel type transistor.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A hall element control circuit, connected to a hall element via a wiring member, for controlling the hall element, the hall element control circuit comprising:
 a first terminal for supplying a bias voltage to a high-potential-side input terminal of the hall element; 
 a second terminal final for supplying a ground potential to a low-potential-side input terminal of the hall element; 
 a first transistor whose source terminal is connected to a power supply potential and whose drain terminal is connected to said first terminal; and 
 an operational amplifier for controlling a gate voltage of said first transistor by differentially amplifying a voltage between a predetermined set voltage and a voltage at said first terminal; and 
 a second transistor and a resistor connected in series with each other so as to constitute a current mirror circuit together with a first series circuit where said first transistor and the hall element are connected in series with each other, 
 wherein said operational amplifier uses a connection point voltage between the second transistor and the resistor as a mirror voltage of high-potential-side input terminal voltage of the hall element. 
 
     
     
       2. A hall element control circuit according to  claim 1 , further comprising:
 a third terminal for receiving a supply of a high-potential-side output voltage of the hall element; and 
 a fourth terminal for receiving a supply of a low-potential-side output voltage of the hall element. 
 
     
     
       3. A hall element control circuit according to  claim 1 , wherein said wiring member is configured by four wirings, used to transmit an input-output voltage of the hall element, which are:
 (1) a wiring that transmits the bias voltage from said hall element control circuit to the hall element; 
 (2) a wiring that transmits a positive-potential-side output voltage from the hall element to said hall element control circuit; 
 (3) a wiring that transmits a negative-potential-side output voltage from the hall element to said hall element control circuit; and 
 (4) a ground wiring.

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