US8773294B2ActiveUtilityA1

Background techniques for comparator calibration

58
Assignee: KOSIC STEPHEN RPriority: Jun 7, 2012Filed: Jun 7, 2012Granted: Jul 8, 2014
Est. expiryJun 7, 2032(~5.9 yrs left)· nominal 20-yr term from priority
H03M 1/167H03M 1/765H03M 1/1023
58
PatentIndex Score
3
Cited by
24
References
20
Claims

Abstract

A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal, comprising:
 calculating a digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages; 
 comparing the value of the residue signal to at least one threshold; 
 based on the comparison, adjusting a triggering threshold of a selected comparator in the first stage; and 
 selecting a highest threshold level comparator that was triggered in response to an input signal that caused the residue signal, as the selected comparator. 
 
     
     
       2. The method of  claim 1 , wherein the at least one threshold includes an upper threshold and a lower threshold, the upper threshold being greater than the lower threshold. 
     
     
       3. The method of  claim 2 , wherein the adjusting includes:
 lowering the triggering threshold when the residue signal is greater than the upper threshold; and 
 raising the triggering threshold when the residue signal is less than the lower threshold. 
 
     
     
       4. The method of  claim 2 , wherein:
 the circuit is an analog-to-digital converter; 
 the upper threshold is approximately +FS; and 
 the lower threshold is approximately −FS, 
 where FS is a full scale value of the converter. 
 
     
     
       5. The method of  claim 1 , wherein the digital value of the residue signal is calculated by combining outputs from all stages subsequent to the first stage. 
     
     
       6. The method of  claim 1 , wherein the adjusting includes changing a tap point in a resistor ladder connected to an input of the selected comparator. 
     
     
       7. The method of  claim 1 , wherein the method is repeatedly performed, using stages from only a portion of the plurality of stages nearest the input signal as the first stage. 
     
     
       8. The method of  claim 1 , wherein the method is performed after adjusting the triggering threshold of the selected comparator using a foreground calibration technique. 
     
     
       9. The method of  claim 1 , wherein the selected comparator has a pair of complementary inputs and the adjusting includes changing both inputs by the same amount, but in opposite directions. 
     
     
       10. The method of  claim 1 , wherein the circuit is an analog-to-digital converter, the method further comprising:
 selecting the comparator based on a digital approximation of an analog input from which the residue signal output by the first stage was generated. 
 
     
     
       11. A device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal, comprising:
 a controller configured to:
 calculate a digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages; 
 compare the value of the residue signal to at least one threshold; and 
 based on the comparison, adjust a triggering threshold of a selected comparator in the first stage, 
 wherein the selected comparator is a highest threshold level comparator that was triggered in response to an input signal that caused the residue signal. 
 
 
     
     
       12. The device of  claim 11 , wherein the at least one threshold includes an upper threshold and a lower threshold, the upper threshold being greater than the lower threshold. 
     
     
       13. The device of  claim 12 , wherein the adjusting includes:
 lowering the triggering threshold when the residue signal is greater than the upper threshold; and 
 raising the triggering threshold when the residue signal is less than the lower threshold. 
 
     
     
       14. The device of  claim 12 , wherein:
 the circuit is an analog-to-digital converter; 
 the upper threshold is approximately +FS; and 
 the lower threshold is approximately −FS, 
 where FS is a full scale value of the converter. 
 
     
     
       15. The device of  claim 11 , wherein the controller calculates the digital value of the residue signal by combining outputs from all stages subsequent to the first stage. 
     
     
       16. The device of  claim 11 , wherein the adjusting includes changing a tap point in a resistor ladder connected to an input of the selected comparator. 
     
     
       17. The device of  claim 11 , wherein the controller repeatedly performs the calculating, the comparing and the adjusting, using stages from only a portion of the plurality of stages nearest the input signal as the first stage. 
     
     
       18. The device of  claim 11 , wherein the controller performs the adjusting after the triggering threshold of the selected comparator is adjusted using a foreground calibration technique. 
     
     
       19. The device of  claim 11 , wherein the selected comparator has a pair of complementary inputs and the adjusting includes changing both inputs by the same amount, but in opposite directions. 
     
     
       20. The device of  claim 11 , wherein the circuit is an analog-to-digital converter, wherein the controller selects the comparator based on a digital approximation of an analog input from which the residue signal output by the first stage was generated.

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