Vertical switch three-dimensional memory array

Abstract

Methods of forming memory devices include providing a substrate, forming source, channel, and drain layers over the substrate, and patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F 2 . The channel layer has a doping type different from a doping type of the source layer, and the drain layer has a doping type different from a doping type of the channel layer.

What is claimed is: 
     
       1. A method of forming a memory device, the method comprising:
 providing a substrate; 
 forming a source layer on the substrate; 
 forming a channel layer over the source layer, the channel layer having a doping type different from a doping type of the source layer; 
 forming a drain layer over the channel layer, the drain layer having a doping type different from a doping type of the channel layer; and 
 patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F 2 , 
 wherein patterning the source, channel, and drain layers comprises:
 forming a plurality of generally parallel isolation trenches intersecting the source, channel, and drain layers; 
 depositing a dielectric material into the plurality of isolation trenches; and 
 planarizing the dielectric material such that a top surface of the dielectric material is substantially coplanar with a top surface of the drain layer. 
 
 
     
     
       2. The method of  claim 1 , wherein patterning the source, channel, and drain layers further comprises:
 forming a plurality of generally parallel gate trenches intersecting the isolation trenches, 
 wherein each memory switch is bounded by intersecting isolation trenches and gate trenches. 
 
     
     
       3. The method of  claim 2 , wherein the cross-sectional area of each memory switch is less than approximately 4 F 2 . 
     
     
       4. The method of  claim 2 , further comprising:
 forming a gate dielectric in contact with the channel layer within the gate trenches; 
 depositing a gate contact material in the gate trenches; and 
 planarizing the gate contact material such that a top surface of the gate contact material is substantially coplanar with a top surface of the dielectric material in the isolation trenches. 
 
     
     
       5. The method of  claim 1 , wherein forming the source, channel, and drain layers each comprises ion implantation of dopants into the substrate. 
     
     
       6. The method of  claim 1 , wherein forming the source, channel, and drain layers each comprises deposition of a semiconductor material over the substrate. 
     
     
       7. The method of  claim 1 , further comprising, substantially simultaneously with patterning the source, channel, and drain layers into an array of memory switches, patterning the source, channel, and drain layers into a plurality of peripheral devices disposed proximate the array of memory switches. 
     
     
       8. The method of  claim 7 , further comprising electrically connecting the peripheral devices to the array of memory switches. 
     
     
       9. The method of  claim 1 , further comprising:
 forming a conductive post over a memory switch; and 
 forming a programmable material in contact with the conductive post, thereby forming a programmable memory cell. 
 
     
     
       10. The method of  claim 9 , wherein the programmable material comprises at least one of phase-change material, a resistive-change material, or a one-time-programmable material. 
     
     
       11. The method of  claim 9 , wherein forming the programmable material comprises etching at least a portion of a dielectric material disposed around the conductive post to form a recess, at least substantially filling the recess with the programmable material, and planarizing the programmable material such that a top surface of the programmable material is substantially coplanar with a top surface of the conductive post. 
     
     
       12. The method of  claim 11 , wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only one corner of the conductive post. 
     
     
       13. The method of  claim 11 , wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only two corners of the conductive post. 
     
     
       14. The method of  claim 1 , wherein the cross-sectional area of each memory switch is less than approximately 4 F 2 . 
     
     
       15. The method of  claim 1 , wherein the memory switches comprise four-layer diodes. 
     
     
       16. The method of  claim 1 , wherein the memory switches comprise MOS transistors. 
     
     
       17. A method of forming a memory device, the method comprising:
 providing a substrate; 
 forming a source layer on the substrate; 
 forming a channel layer over the source layer, the channel layer having a doping type different from a doping type of the source layer; 
 forming a drain layer over the channel layer, the drain layer having a doping type different from a doping type of the channel layer; 
 patterning the source, channel, and drain layers into an array of memory switches each having a cross-sectional area less than 6 F 2 ; 
 forming a conductive post over a memory switch; and 
 forming a programmable material in contact with the conductive post, thereby forming a programmable memory cell. 
 
     
     
       18. The method of  claim 17 , wherein the programmable material comprises at least one of phase-change material, a resistive-change material, or a one-time-programmable material. 
     
     
       19. The method of  claim 17 , wherein forming the programmable material comprises etching at least a portion of a dielectric material disposed around the conductive post to form a recess, at least substantially filling the recess with the programmable material, and planarizing the programmable material such that a top surface of the programmable material is substantially coplanar with a top surface of the conductive post. 
     
     
       20. The method of  claim 19 , wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only one corner of the conductive post. 
     
     
       21. The method of  claim 19 , wherein the conductive post has a substantially quadrilateral cross-sectional area, and the programmable material is disposed in contact with only two corners of the conductive post. 
     
     
       22. The method of  claim 17 , wherein patterning the source, channel, and drain layers comprises:
 forming a plurality of generally parallel isolation trenches intersecting the source, channel, and drain layers; 
 depositing a dielectric material into the plurality of isolation trenches; 
 planarizing the dielectric material such that a top surface of the dielectric material is substantially coplanar with a top surface of the drain layer; and 
 forming a plurality of generally parallel gate trenches intersecting the isolation trenches, 
 wherein each memory switch is bounded by intersecting isolation trenches and gate trenches. 
 
     
     
       23. The method of  claim 22 , further comprising:
 forming a gate dielectric in contact with the channel layer within the gate trenches; 
 depositing a gate contact material in the gate trenches; and 
 planarizing the gate contact material such that a top surface of the gate contact material is substantially coplanar with a top surface of the dielectric material in the isolation trenches. 
 
     
     
       24. The method of  claim 17 , wherein the cross-sectional area of each memory switch is less than approximately 4 F 2 . 
     
     
       25. The method of  claim 17 , wherein forming the source, channel, and drain layers each comprises ion implantation of dopants into the substrate. 
     
     
       26. The method of  claim 17 , wherein forming the source, channel, and drain layers each comprises deposition of a semiconductor material over the substrate. 
     
     
       27. The method of  claim 17 , further comprising, substantially simultaneously with patterning the source, channel, and drain layers into an array of memory switches, patterning the source, channel, and drain layers into a plurality of peripheral devices disposed proximate the array of memory switches. 
     
     
       28. The method of  claim 27 , further comprising electrically connecting the peripheral devices to the array of memory switches. 
     
     
       29. The method of  claim 17 , wherein the memory switches comprise four-layer diodes. 
     
     
       30. The method of  claim 17 , wherein the memory switches comprise MOS transistors.