Methods of manufacturing lateral diffused MOS devices with layout controlled body curvature and related devices

Abstract

The present invention discloses a method of manufacturing an N-type LDMOS device. The method comprises forming a gate above the semiconductor substrate; forming a body, comprising forming a Pwell apart from the gate and forming a Pbase partly in the Pwell, wherein the Pbase is wider and shallower than the Pwell; and forming an N-type source and a drain contact region. Wherein the body curvature of the LDMOS device is controlled by adjusting the layout width of the Pwell.

I claim: 
     
       1. A method of forming a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device in a semiconductor substrate wherein the semiconductor substrate has a top surface, the method comprising:
 forming a gate above the semiconductor substrate; 
 forming a body having a body curvature, comprising:
 forming a well in the semiconductor substrate from the top surface, wherein the well is of a first doping type; 
 forming a base region of a first doping type from the top surface, wherein the base region is formed partly in the well, and wherein the base region is wider and shallower than the well; and 
 
 forming a source region and a drain contact region of a second doping type, wherein the source region is adjacent to the body at one side of the gate and wherein the drain contact region is at another side of the gate; 
 and wherein the body curvature defined by outlines of the well and the base region is controlled by adjusting the layout width of the well; and wherein 
 the layout width of the well is increased to increase a breakdown voltage of the LDMOS device. 
 
     
     
       2. The method of  claim 1 , wherein the layout width of the well is adjusted having a negative relationship with the body curvature. 
     
     
       3. The method of  claim 1 , wherein the layout width of the well is increased to decrease the body curvature. 
     
     
       4. The method of  claim 1 , further comprising forming a well of a second doping type in the semiconductor substrate, wherein said well of a second doping type is formed from the top surface, and wherein the body is formed in said well of a second doping type. 
     
     
       5. The method of  claim 1 , wherein the base region is formed self-aligned to the edge of the gate. 
     
     
       6. The method of  claim 5 , further comprising forming a channel region by performing a thermal annealing step to side diffuse the base region under the gate, and wherein the source region is formed self-aligned to the gate. 
     
     
       7. The method of  claim 1 , further comprising forming a second well of a second doping type, wherein the second well is formed using the well of the first doping type as a counter-part. 
     
     
       8. The method of  claim 7 , wherein forming the second well comprises:
 forming an oxide layer self-aligned to the well of the first doping type; 
 forming a well of a second doping type using the oxide layer serving as a blocking mask; and 
 performing a thermal annealing step to side diffuse said well of a second doping type under the well of the first doping type. 
 
     
     
       9. The method of  claim 1 , wherein the first doping type is P type. 
     
     
       10. A method of forming a Lateral Diffused Metal Oxide Semiconductor (LDMOS) device in a semiconductor substrate wherein the semiconductor substrate has a top surface, the method comprising:
 forming a first well of a first doping type in the semiconductor substrate from the top surface, wherein the first well is configured to have a layout space; 
 forming a body having a body curvature, comprising:
 forming a second well of a second doping type in the semiconductor substrate from the top surface, wherein the second well is formed in the layout space of the first well; 
 forming a base region of a second doping type from the top surface, wherein the base region is formed partly in the second well of the second doping type, and wherein the base region is wider and shallower than the second well; 
 
 forming a gate above the semiconductor substrate; and 
 forming a source and a drain contact region of a first doping type, wherein the source is formed at one side of the gate and the drain contact region is formed at another side of the gate; 
 and wherein the body curvature defined by outlines of the second well and the base region is controlled by adjusting the layout space width of the first well; and wherein 
 the layout space width of the first well is adjusted having a negative relationship with the body curvature. 
 
     
     
       11. The method of  claim 10 , wherein forming the second well further comprising:
 forming an oxide layer self-aligned to the first well; and 
 forming the second well in the layout space using the oxide layer serving as a blocking mask. 
 
     
     
       12. The method of  claim 11 , further comprising performing a thermal annealing step after forming the second well. 
     
     
       13. The method of  claim 10 , further comprising forming a channel region by performing a thermal annealing step to side diffuse the base region under the gate. 
     
     
       14. The method of  claim 10 , wherein the first doping type is N type and the second doping type is P type. 
     
     
       15. A semiconductor device, comprising a LDMOS device integrated into a semiconductor substrate, wherein the LDMOS device comprises:
 a gate above the semiconductor substrate; 
 a body having a body curvature, the body comprising:
 a well of a first doping type having a lateral width; 
 a base of a first doping type, wherein the base is partly in the well, and
 wherein the base is shallower than the well; 
 
 
 a source of a second doping type abutting the body, wherein the source is at one side of the gate and wherein the source is self-aligned to the gate; and 
 a drain contact region of a second doping type at another side of the gate; 
 wherein the body curvature has a negative relationship with the lateral width of the well. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein the well has a first lateral width and a first depth, and wherein the semiconductor device further comprises an other region, the other region having a second well of a first doping type, and the second well having a second lateral width and a second depth, wherein the first lateral width is larger than the second lateral width, and wherein the first depth is larger than the second depth. 
     
     
       17. The semiconductor device of  claim 15 , wherein the well has a first lateral width and a first depth, and wherein the semiconductor device further comprises an other region, the other region having a second well of a first doping type, and the second well having a second lateral width and a second depth, wherein the first lateral width is smaller than the second lateral width, and wherein the first depth is smaller than the second depth. 
     
     
       18. The semiconductor device of  claim 15 , wherein the first doping type is P type.