Non-volatile semiconductor memory device performing multi-level storage operation

Abstract

A non-volatile semiconductor memory device includes: a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and a controller to control the memory unit, wherein the controller sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; assigns the first state to the error correction bits that correspond to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bits that correspond to the data state having other threshold level; and resets the error correction bit to the first state when the error correction bit indicates the second state.

What is claimed is: 
     
       1. A non-volatile semiconductor memory device comprising:
 a memory unit including a plurality of memory cells, each of the plurality of memory cells to perform a multi-level storage operation by assigning a value including a plurality of bits to at least four data states defined according to a threshold level; and 
 a controller to control the memory unit, wherein the controller 
 sets at least one of the plurality of bits to an error correction bit that indicates one of a first state and a second state; 
 assigns the first state to the error correction bit that corresponds to the data states having a minimum threshold level and a maximum threshold level and the second state to the error correction bit that corresponds to the data states having other threshold level; 
 sets the error correction bit to the first state when writing data in at least one of the plurality of memory cells; and 
 resets the error correction bit to the first state if the error correction bit indicates the second state when reading the error correction bit periodically. 
 
     
     
       2. The non-volatile semiconductor memory device according to  claim 1 , wherein the first state indicates a normal state and the second state indicates an abnormal state. 
     
     
       3. The non-volatile semiconductor memory device according to  claim 1 , wherein the controller sets the other bit, which is included in the plurality of bits and is other than the at least one of the plurality of bits, to a data bit. 
     
     
       4. The non-volatile semiconductor memory device according to  claim 1 , wherein the memory unit includes a plurality of memory cell groups, each of the plurality of memory cell groups being a unit of reading and including a plurality of memory cells; and each of the plurality of memory cell groups is assigned with at least two page addresses including a first page address designating data bits and a second page address designating the error correction bits. 
     
     
       5. The non-volatile semiconductor memory device according to  claim 1 , wherein the memory unit is a NAND flash memory. 
     
     
       6. The non-volatile semiconductor memory device according to  claim 4 , wherein when at least one of a plurality of memory cells, which corresponds to the second page address of a first memory cell group of the plurality of memory cell groups, is in the second state, the controller reads data in the first page address of the first memory cell group, writes the data in the first page address of a second memory cell group of the plurality of memory cell groups, and sets a plurality of memory cells in the second page address of the second memory cell group to the first state. 
     
     
       7. The non-volatile semiconductor memory device according to  claim 4 , further comprising: an address table of associated logical addresses given externally with the first page addresses. 
     
     
       8. The non-volatile semiconductor memory device according to  claim 7  wherein the controller writes data in the first page address corresponding to the logical address obtained from the address table, and sets a plurality of memory cells in the second page address to the first state, the second address being assigned to the memory cell group that corresponds to the first page address. 
     
     
       9. The non-volatile semiconductor memory device according to  claim 7  wherein the controller reads data from the first page address corresponding to the logical address obtained from the address table. 
     
     
       10. The non-volatile semiconductor memory device according to  claim 1  wherein each of the plurality of memory cells includes a floating gate transistor, and a state of the memory cell is determined in response to an amount of electrical charge stored in a floating gate.