Programmable structured arrays

Abstract

A programmable semiconductor device includes a user programmable switch comprising a configurable element positioned above a transistor material layer deposited on a substrate layer.

What is claimed is: 
     
       1. A device comprising:
 a layer comprising a pass-gate and a configuration circuit coupled to said pass-gate, wherein said pass-gate is configured to receive an output of said configuration circuit; 
 a first metal line; and 
 a second metal line; 
 said pass-gate configured to electrically connect said first and second metal lines and configured to electrically disconnect said first and second metal lines, according to a state of said output. 
 
     
     
       2. The device of  claim 1 , wherein said pass-gate and said configuration circuit comprise thin film transistors (TFTs). 
     
     
       3. The device of  claim 1 , wherein said first metal line and said second metal line are both located on one side of said layer. 
     
     
       4. The device of  claim 1 , wherein said first metal line and said second metal line are located on opposite sides of said layer. 
     
     
       5. The device of  claim 1 , wherein said configuration circuit comprises a memory element, wherein said output comprises a control signal that has a first voltage level if said memory element has a first polarity and a second voltage level if said memory element has a second polarity. 
     
     
       6. The device of  claim 1 , wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating. 
     
     
       7. The device of  claim 1 , further comprising:
 a first through-hole via connecting said pass-gate at one end to said first metal line; and 
 a second through-hole via connecting said pass-gate at another end to said second metal line. 
 
     
     
       8. A structure comprising:
 a first plurality of wires including a first wire; 
 a second plurality of wires including a second wire; and 
 a plurality of pass-gates coupled to said first plurality of wires and to said second plurality of wires, said plurality of pass-gates including a pass-gate coupled at one end to said first wire and at another end to said second wire, said pass-gate also coupled to a configuration circuit, wherein said pass-gate and said configuration circuit are in a same layer of said structure; wherein said first wire is configured to be electrically connected to and electrically disconnected from said second wire responsive to turning on and turning off said pass-gate according to a state of an output of said configuration circuit. 
 
     
     
       9. The structure of  claim 8 , wherein said configuration circuit comprises a memory element, wherein said output comprises a control signal that has a first voltage level if said memory element has a first polarity and a second voltage level if said memory element has a second polarity. 
     
     
       10. The structure of  claim 8 , wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of: fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating. 
     
     
       11. The structure of  claim 8 , wherein said first plurality of wires and said second plurality of wires are configured to be electrically interconnected in a pattern responsive to selectively turning on a first subset of said plurality of pass-gates and selectively turning off a second subset of said plurality of pass-gates. 
     
     
       12. The structure of  claim 11 , wherein said configuration circuit comprises a plurality of memory elements coupled to said plurality of pass-gates, wherein said first subset of pass-gates is configured to be turned on and said second subset of pass-gates is configured to be turned off according to bit values stored in said memory elements. 
     
     
       13. The structure of  claim 12 , wherein said bit values are programmable and wherein said pattern is changeable in response to a change in said bit values. 
     
     
       14. A structure comprising:
 a first layer comprising a first plurality of wires; 
 a second layer comprising a second plurality of wires; 
 a third layer between said first layer and said second layer and comprising a plurality of pass-gates and a configuration circuit; wherein said pass-gates are configured to be selectively turned on to enable one or more types of electrical connections, said types of electrical connections comprising: an electrical connection between two wires in said first layer; an electrical connection between two wires in said second layer; and an electrical connection between a wire in said first layer and a wire in said second layer. 
 
     
     
       15. The structure of  claim 14 , wherein said pass-gates and said configuration circuit comprise thin film transistors (TFTs). 
     
     
       16. The structure of  claim 14 , wherein said configuration circuit comprises a type of memory circuit selected from the group consisting of: fuse, anti-fuse, EPROM, EEPROM, flash, ferro-electric, magnetic, SRAM, DRAM, metal optional, optical, laser fuse, photo-electric, electro-chemical, electrolytic, carbon nanotube, electro-mechanical, electro-magnetic, and resistance modulating. 
     
     
       17. The structure of  claim 14 , further comprising:
 a first plurality of through-hole vias coupled to pass-gates in said third layer and to wires in said first layer; and 
 a second plurality of through-hole vias coupled to pass-gates in said third layer and to wires in said second layer. 
 
     
     
       18. The structure of  claim 14 , wherein said first plurality of wires and said second plurality of wires are configured to be electrically interconnected in a pattern responsive to selectively turning on a first subset of said plurality of pass-gates and selectively turning off a second subset of said plurality of pass-gates. 
     
     
       19. The structure of  claim 18 , wherein said configuration circuit comprises a plurality of memory elements coupled to said plurality of pass-gates, wherein said first subset of pass-gates is configured to be turned on and said second subset of pass-gates is configured to be turned off in response to bit values stored in said memory elements. 
     
     
       20. The structure of  claim 19 , wherein said bit values are programmable and wherein said pattern is changeable in response to a change in said bit values.