Input unit cell circuitry for transducer readout

Abstract

Techniques are disclosed that provide time delay integration (TDI) in detection signal processing (such as a signal generated by an IR sensor). The techniques can be implemented, for example, to provide blanking and/or TDI functionality at the readout integrated circuit (ROIC) level for active focal plane array (FPA) elements or other transducer elements. In one example embodiment, an integrator circuit is configured with one or more switches for allowing integration of multiple input signal events such that reset of the integration is controlled independently and can be reset equal to or less often than the number of single events, thereby allowing one or more detected events to be integrated together within a frame interval.

What is claimed is: 
     
       1. An electronic device comprising:
 an amplifier having an inverting input and an output, the inverting input for receiving input from a transducer; 
 an integration capacitor operatively connected between the inverting input and the output, and for integrating signal from the transducer during an integration cycle; 
 a first switch operatively coupled to the inverting input and for selectively opening to interrupt integration of signal from the transducer, so as to provide an interrupt point in the integration cycle; and 
 a second switch operatively coupled to the first switch and for selectively applying a bias voltage to the transducer when the first switch is open and for selectively opening upon subsequent closure of the first switch to resume the previously interrupted integration cycle from the interrupt point. 
 
     
     
       2. The device of  claim 1  further comprising a reset switch operatively coupled between the output of the amplifier and the inverting input. 
     
     
       3. The device of  claim 2  wherein a non-inverting input of the amplifier is configured to receive a bias voltage that sets a reset voltage that will be presented at the amplifier output during a reset interval. 
     
     
       4. The device of  claim 2  wherein a timing scheme of the first, second, and reset switches allows a plurality of integration intervals to occur prior to a next reset interval. 
     
     
       5. The device of  claim 1  wherein the bias voltage maintains the voltage across the transducer to be within 5% of the first voltage. 
     
     
       6. The device of  claim 1  further comprising the transducer, wherein the transducer is a photo sensitive detector. 
     
     
       7. The device of  claim 1  further comprising the transducer, wherein the first switch and the second switch do not close in an overlapping fashion. 
     
     
       8. The device of  claim 1  wherein a timing scheme of the first and second switches defines a plurality of integration intervals of different duration. 
     
     
       9. The device of  claim 1  wherein a timing scheme of the first and second switches defines one or more blanking intervals where the amplifier does not integrate input signal events. 
     
     
       10. A read-out integrated circuit (ROIC) comprising the electronic device of  claim 1 . 
     
     
       11. A sensor system comprising the ROIC of  claim 10  wherein the system includes a transducer array operatively coupled to the ROIC. 
     
     
       12. A system-on-chip comprising the sensor system of  claim 11 . 
     
     
       13. An integrated circuit, comprising:
 a transducer array; 
 an amplifier having an inverting input and an output, the inverting input for receiving input from an element of the transducer array; 
 an integration capacitor operatively connected between the inverting input and the output, and for integrating signal from the element of the transducer array during an integration cycle; 
 a reset switch operatively coupled across the integration capacitor; 
 a first switch operatively coupled to the inverting input and for selectively opening to interrupt integration of signal from the element of the transducer array, so as to provide an interrupt point in the integration cycle; and 
 a second switch operatively coupled to the transducer array and for selectively applying a bias voltage to the transducer array when the first switch is open and for selectively opening upon subsequent closure of the first switch to resume the previously interrupted integration cycle from the interrupt point; 
 wherein the first and second switches do not close in an overlapping fashion. 
 
     
     
       14. The integrated circuit of  claim 13  wherein a non-inverting input of the amplifier is configured to receive a bias voltage that sets a reset voltage that will be presented at the amplifier output during a reset interval. 
     
     
       15. The integrated circuit of  claim 13  wherein a timing scheme of the first, second, and reset switches allows a plurality of integration intervals to occur prior to a next reset interval. 
     
     
       16. The integrated circuit of  claim 13  wherein the transducer array comprises a plurality of photo sensitive detector elements. 
     
     
       17. The integrated circuit of  claim 13  wherein the transducer array comprises a plurality of sensor elements each of which generates a current in response to a stimulus. 
     
     
       18. The integrated circuit of  claim 13  wherein a timing scheme of the first and second switches defines a plurality of integration intervals of different duration. 
     
     
       19. A sensing system, comprising:
 a transducer array; 
 an amplifier having an inverting input, a non-inverting input, and an output, the inverting input for receiving input from an element of the transducer array, wherein the non-inverting input is configured to receive a bias voltage that sets a reset voltage that will be presented at the amplifier output during a reset interval; 
 an integration capacitor operatively connected between the inverting input and the output, and for integrating signal from the element of the transducer array during an integration cycle; 
 a reset switch operatively coupled across the integration capacitor; 
 a first switch operatively coupled to the inverting input and for selectively opening to interrupt integration of signal from the element of the transducer array, so as to provide an interrupt point in the integration cycle; and 
 a second switch operatively coupled to the transducer array and for selectively applying a bias voltage to the transducer array when the first switch is open and for selectively opening upon subsequent closure of the first switch to resume the previously interrupted integration cycle from the interrupt point; 
 wherein a timing scheme of the first, second, and reset switches allows for:
 a plurality of integration intervals to occur prior to a next reset interval; and 
 a plurality of blanking intervals where the amplifier does not integrate input signal events. 
 
 
     
     
       20. The system of  claim 19  wherein the transducer array comprises a plurality of photo sensitive detector elements or piezoelectric sensor elements.