Noise reduction and tilt reduction in passive FET multi-phase mixers

Abstract

The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.

What is claimed is: 
     
       1. A passive mixer circuit comprising at least a first mixer branch, the first mixer branch comprising:
 first and second switching transistors connected from a first output signal terminal to first and second input signal terminals, respectively, and arranged to be switched on by active levels of first and second local oscillator, (LO) signals, respectively; 
 third and fourth switching transistors connected from a second output signal terminal to the first and second input signal terminals, respectively, and arranged to be switched on by active levels of the second and first LO signals, respectively; 
 
       wherein said passive mixer circuit is characterized by further comprising:
 a local oscillator, (LO) circuit arranged to provide the first and second LO signals at an LO frequency, so that each of the first and second LO signals has an active-level duty cycle of less than 50% and so that the first and second LO signals are separated so as to form first inactive intervals in which neither of the first and second LO signals is at an active level, and to provide third and fourth, non-overlapping, LO signals at the LO frequency and that are each at active levels only during respective alternating ones of the first inactive intervals; and 
 one or more high-side bypass switches connected between a circuit ground and the first input signal terminal and one or more low-side bypass switches connected between the circuit ground and the second input signal terminal, wherein the bypass switches are arranged so that at least one of the high-side bypass switches and at least one of the low-side bypass switches are activated, by the third and fourth LO signals, during each of the first inactive intervals. 
 
     
     
       2. The passive mixer circuit of  claim 1 , wherein the LO circuit is arranged to provide each of the first, second, third, and fourth LO signals with a duty cycle of approximately 25% and with the third and fourth LO signals leading the second and first LO signals, respectively, by 90 degrees. 
     
     
       3. The passive mixer circuit of  claim 1 , wherein the LO circuit is arranged to provide each of the third and fourth LO signals with a duty cycle of about 12.5% or less. 
     
     
       4. The passive mixer circuit of  claim 1 , wherein:
 the high-side bypass switches comprise a first bypass transistor connected between the first input signal terminal and the circuit ground, proximate to the first switching transistor and arranged so as to be activated by the fourth LO signal, and a second bypass transistor connected between the first input signal terminal and the circuit ground, proximate to the third switching transistor and arranged so as to be activated by the third LO signal; and 
 the low-side bypass switches comprise a third bypass transistor connected between the second input signal terminal and the circuit ground, proximate to the second switching transistor and arranged so as to be activated by the third LO signal, and a fourth bypass transistor connected between the second input signal terminal and the circuit ground, proximate to the fourth switching transistor and arranged so as to be activated by the fourth LO signal. 
 
     
     
       5. The passive mixer circuit of  claim 1 , further comprising one or more output bypass switches connected between a circuit ground and the first signal output terminal, and one or more additional output bypass switches connected between the circuit ground and the second signal output terminal, wherein the output bypass switches and additional output bypass switches are arranged so that at least one of the output bypass switches and at least one of the additional output bypass switches are activated, by the third and fourth LO signals, during each of the first inactive intervals. 
     
     
       6. The passive mixer circuit of  claim 5 , wherein:
 the output bypass switches comprise a first output bypass transistor connected between the first output signal terminal and the circuit ground, proximate to the first switching transistor and arranged so as to be activated by the fourth LO signal, and a second output bypass transistor connected between the first output signal terminal and the circuit ground, proximate to the second switching transistor and arranged so as to be activated by the third LO signal; and 
 the additional output bypass switches comprise a third output bypass transistor connected between the second output signal terminal and the circuit ground, proximate to the third switching transistor and arranged so as to be activated by the third LO signal, and a fourth output bypass transistor connected between the second output signal terminal (IF−) and the circuit ground, proximate to the fourth switching transistor, and arranged so as to be activated by the fourth LO signal. 
 
     
     
       7. The passive mixer circuit of  claim 1 , further comprising a second mixer branch arranged to provide a quadrature output at first and second quadrature output signal terminals, the second mixer branch comprising:
 fifth and sixth switching transistors connected from the first quadrature output signal terminal to the first input signal terminal and the second input signal terminal, respectively, and arranged to be switched on by active levels of the third and fourth LO signals, respectively; 
 seventh and eighth switching transistors connected from the second quadrature output signal terminal to the first input signal terminal and the second input signal terminal, respectively, and arranged to be switched on by the fourth and third LO signals, respectively; and 
 one or more additional high-side bypass switches connected between the circuit ground and the first input signal terminal, and one or more additional low-side bypass switches connected between the circuit ground and the second input signal terminal, wherein the additional high-side and low-side bypass switches are arranged so that at least one of the additional high-side bypass switches and at least one of the additional low-side bypass switches are activated by active levels of the first and second LO signals. 
 
     
     
       8. The passive mixer circuit of  claim 1 , wherein the LO circuit is arranged to provide each of the first, second, third, and fourth LO signals with a duty cycle of approximately 12.5% and with the third and fourth LO signals leading the second and first LO signals, respectively, by 45 degrees. 
     
     
       9. A wireless communication device having a communication interface for wireless communicating with a remote communication device, the communication interface including a passive mixer circuit having at least a first mixer branch, the first mixer branch comprising:
 first and second switching transistors connected from a first output signal terminal to first and second input signal terminals, respectively, and arranged to be switched on by active levels of first and second local oscillator, (LO) signals, respectively; 
 third and fourth switching transistors connected from a second output signal terminal to the first and second input signal terminals, respectively, and arranged to be switched on by active levels of the second and first LO signals, respectively; 
 
       wherein said passive mixer circuit is characterized by further comprising:
 a local oscillator, (LO) circuit arranged to provide the first and second LO signals at an LO frequency, so that each of the first and second LO signals has an active-level duty cycle of less than 50% and so that the first and second LO signals are separated so as to form first inactive intervals in which neither of the first and second LO signals is at an active level, and to provide third and fourth, non-overlapping, LO signals at the LO frequency and that are each at active levels only during respective alternating ones of the first inactive intervals; and 
 one or more high-side bypass switches connected between a circuit ground and the first input signal terminal and one or more low-side bypass switches connected-between the circuit ground and the second input signal terminal, wherein the bypass switches are arranged so that at least one of the high-side bypass switches and at least one of the low-side bypass switches are activated, by the third and fourth LO signals, during each of the first inactive intervals. 
 
     
     
       10. The wireless communication device of  claim 9 , wherein the LO circuit is arranged to provide each of the first, second, third, and fourth LO signals with a duty cycle of approximately 25% and with the third and fourth LO signals leading the second and first LO signals, respectively, by 90 degrees. 
     
     
       11. The wireless communication device of  claim 9 , wherein the LO circuit is arranged to provide each of the third and fourth LO signals with a duty cycle of about 12.5% or less. 
     
     
       12. The wireless communication device of  claim 9 , wherein:
 the high-side bypass switches comprise a first bypass transistor connected between the first input signal terminal and the circuit ground, proximate to the first switching transistor and arranged so as to be activated by the fourth LO signal, and a second bypass transistor connected between the first input signal terminal and the circuit ground, proximate to the third switching transistor and arranged so as to be activated by the third LO signal; and 
 the low-side bypass switches comprise a third bypass transistor connected between the second input signal terminal (RF−) and the circuit ground, proximate to the second switching transistor and arranged so as to be activated by the third LO signal, and a fourth bypass transistor connected between the second input signal terminal and the circuit ground, proximate to the fourth switching transistor and arranged so as to be activated by the fourth LO signal. 
 
     
     
       13. The wireless communication device of  claim 9 , further comprising one or more output bypass switches connected between a circuit ground and the first signal output terminal, and one or more additional output bypass switches connected-between the circuit ground and the second signal output terminal, wherein the output bypass switches and additional output bypass switches are arranged so that at least one of the output bypass switches and at least one of the additional output bypass switches are activated, by the third and fourth LO signals, during each of the first inactive intervals. 
     
     
       14. The wireless communication device of  claim 13 , wherein:
 the output bypass switches comprise a first output bypass transistor connected between the first output signal terminal and the circuit ground, proximate to the first switching transistor and arranged so as to be activated by the fourth LO signal, and a second output bypass transistor connected between the first output signal terminal and the circuit ground, proximate to the second switching transistor and arranged so as to be activated by the third LO signal; and 
 the additional output bypass switches comprise a third output bypass transistor connected between the second output signal terminal and the circuit ground, proximate to the third switching transistor and arranged so as to be activated by the third LO signal, and a fourth output bypass transistor connected between the second output signal terminal and the circuit ground, proximate to the fourth switching transistor, and arranged so as to be activated by the fourth LO signal. 
 
     
     
       15. The wireless communication device of  claim 9 , wherein the passive mixer circuit further comprises a second mixer branch arranged to provide a quadrature output at first and second quadrature output signal terminals, the second mixer branch comprising:
 fifth and sixth switching transistors connected from the first quadrature output signal terminal to the first input signal terminal and the second input signal terminal, respectively, and arranged to be switched on by active levels of the third and fourth LO signals, respectively; 
 seventh and eighth switching transistors connected from the second quadrature output signal terminal to the first input signal terminal and the second input signal terminal, respectively, and arranged to be switched on by the fourth and third LO signals, respectively; and 
 one or more additional high-side bypass switches connected between the circuit ground and the first input signal terminal, and one or more additional low-side bypass switches connected between the circuit ground and the second input signal terminal, wherein the additional high-side and low-side bypass switches are arranged so that at least one of the additional high-side bypass switches and at least one of the additional low-side bypass switches are activated by active levels of the first and second LO signals. 
 
     
     
       16. The wireless communication device of  claim 9 , wherein the LO circuit is arranged to provide each of the first, second, third, and fourth LO signals with a duty cycle of approximately 12.5% and with the third and fourth LO signals leading the second and first LO signals, respectively, by 45 degrees.