Computer system with bridge

Abstract

A computer system includes a central processing unit (CPU), a north bridge, a south bridge, a bridge and a slot. The north bridge is electrically connected to the CPU. The bridge is electrically connected to the north bridge and the south bridge, and the connector is connected to the bridge. The bridge generates a first data and a second data according to the data packages transmitted from the north bridge and adjusts the output bandwidth of the first data and the second data according to a channel control signal. The south bridge receives or transfers the first data via the bridge so as to communicate with the north bridge. The slot is electrically connected to the bridge and receives or transfers the second data via the bridge so as to communicate with the north bridge.

What is claimed is: 
     
       1. A computer system, comprising:
 a central processing unit (CPU); 
 a north bridge electrically connected to the CPU; 
 a bridge connected to the north bridge and the south bridge for correspondingly generating a first data and a second data according to a data packages transmitted from the north bridge and adjusting an output bandwidth of the first data and the second data, wherein the bridge comprises:
 a data decoder for decoding the data packages transmitted from the north bridge to generate the first data and the second data; 
 a first data encoder for generating a first data package corresponding to the first data; and 
 a second data encoder for generating a second data package corresponding to the second data; 
 
 a south bridge electrically connected to the bridge to receive the first data; and 
 a first slot electrically connected to the bridge to receive the second data and exchanging the data with the north bridge via the bridge. 
 
     
     
       2. The computer system according to  claim 1 , wherein the bridge further comprises:
 a first data buffer for storing the first data package; and 
 a second data buffer for storing the second data package. 
 
     
     
       3. The computer system according to  claim 2 , wherein the bridge further comprises:
 a first channel multiplexer including: 
 an input end electrically connected to the first data buffer to receive the first data package; 
 a control end to receive a channel control signal; and 
 a plurality of the output ends for outputting the first data package, wherein the first channel multiplexer switch the transmission paths between the input end and the output ends according to the channel control signal. 
 
     
     
       4. The computer system according to  claim 2 , wherein the bridge further comprises:
 a second channel multiplexer including: 
 an input end electrically connected to the second data buffer to receive the second data package; 
 a control end for receiving the channel control signal; and 
 a plurality of the output ends for outputting the second data package, wherein the second channel multiplexer switch the transmission paths between the input end and the output ends according to the channel control signal. 
 
     
     
       5. The computer system according; to  claim 1 , wherein the bridge comprises a basic input/output system (BIOS) channel control register for providing a channel control signal, and the bridge adjusts the output bandwidth of the first data and the second data according to the channel control signal. 
     
     
       6. The computer system according to  claim 1 , wherein data is transferred between the north bridge and the bridge via m channels of a first bus, the data is transferred between the south bridge and the bridge via n channels of a second bus, m is a positive integer, and n is a positive integer not larger than m, 
     
     
       7. The computer system according to  claim 6 , wherein the first bus and the second bus are direct media interface (DMI) buses. 
     
     
       8. The computer system according to  claim 7 , wherein the first data conform to DMI bus transferring specification. 
     
     
       9. The computer system according to  claim 6 , wherein the first slot and the bridge transfer the data to each other via p channels of a third bus, and p is a positive integer. 
     
     
       10. The computer system according to  claim 9 , wherein the value of m is the sum of n and p. 
     
     
       11. The computer system according to  claim 9 , wherein the first slot at least comprises a group of peripheral component interconnect express (PCIe) slots. 
     
     
       12. The computer system according to  claim 11 , wherein the first bus and the second bus are DMI buses, and the third bus is a PCIe bus. 
     
     
       13. The computer system according to  claim 12 , wherein the first data conform to DMI bus transferring specification, and the second data conform to PCIe bus transferring specification. 
     
     
       14. The computer system according to  claim 1 , further comprising a second slot transferring data to the north bridge via a fourth bus. 
     
     
       15. The computer system according to  claim 14 , wherein the second slot at east comprises a group of PCIe slots. 
     
     
       16. The computer system according to  claim 15 , wherein the fourth bus is PCle bus.