Power on detection circuit

Abstract

A power-on-detection (POD) circuit includes first and second comparators, a voltage divider, a detection circuit coupled to a first voltage source node and the voltage divider, and logic circuitry coupled to outputs of the first and second comparators. The detection circuit outputs a control signal identifying if a first voltage source node has a voltage potential that is higher than ground. The control signal turns on and off the first and second comparators, which are respectively coupled to first and second nodes of the voltage divider and to a reference voltage node. The logic circuitry outputs a power identification signal based on the signals received from the outputs of the first and second comparators.

What is claimed is: 
     
       1. A power-on-detection (POD) circuit, comprising:
 first and second comparator circuits each having first and second inputs, the first inputs of the first and second comparator circuits receiving a reference voltage from a reference voltage source node; 
 a voltage divider circuit including first, second, and third resistors, the first and second resistors coupled together at a first node, the second and third resistors coupled together at a second node, the first node of the voltage divider is coupled directly to the second input of the first comparator circuit and the second node of the voltage divider circuit is coupled directly to the second input of the second comparator circuit; 
 a detection circuit coupled between a first voltage source node and the first resistor of the voltage divider circuit, the detection circuit generating a control signal in response to the first voltage source node having a voltage potential higher than a ground potential, the control signal controlling the turning on and off of the first and second comparator circuits; and 
 logic circuitry coupled to an output of each of the first and second comparator circuits, the logic circuitry outputting a power identification signal based on the outputs of the first and second comparator circuits and the control signal generated by and received from the detection circuit, 
 wherein the detection circuit includes:
 a first MOS transistor having a source coupled to the first voltage source node; 
 a second MOS transistor having a source and a drain, the drain of the second MOS transistor coupled to a drain of the first MOS transistor: 
 a third MOS transistor having a drain coupled to the first resistor of the voltage divider, a source coupled to the first voltage source node, and a gate coupled to the drains of the first and second MOS transistors at a third node; and 
 a capacitor coupled between the first voltage source node and the third node. 
 
 
     
     
       2. The POD circuit of  claim 1 , wherein the detection circuit includes an inverter coupled to the third node and to the first and second comparator circuits. 
     
     
       3. The POD circuit of  claim 1 , wherein a gate of one of the first and second MOS transistors is coupled to the reference voltage source node. 
     
     
       4. The POD circuit of  claim 1 , wherein the first comparator circuit includes a differential amplifier for generating an output signal identifying if the voltage potential of the first node of the voltage divider is greater than the reference voltage potential. 
     
     
       5. The POD circuit of  claim 4 , wherein the first comparator circuit includes fourth and fifth MOS transistors having respective gates each receiving the control signal. 
     
     
       6. The POD circuit of  claim 1 , wherein the second comparator circuit includes a differential amplifier for generating an output signal identifying if a voltage potential of the second node of the voltage divider is greater than the reference voltage potential. 
     
     
       7. The POD circuit of  claim 6 , wherein the second comparator circuit includes fourth and fifth MOS transistors having respective gates each receiving the control signal. 
     
     
       8. The POD circuit of  claim 7 , wherein each of the fourth and fifth MOS transistors has a decoupling capacitor coupled across a source and a drain. 
     
     
       9. The POD circuit of  claim 1 , wherein the logic circuitry includes an AND gate receiving the control signal directly from the detection circuit as an input. 
     
     
       10. A power-on-detection (POD) circuit, comprising:
 first and second comparator circuits each having first and second inputs, the first inputs of the first and second comparator circuits coupled to a reference voltage node having a reference voltage potential; 
 a voltage divider circuit having first and second nodes, the first node directly coupled to the second input of the first comparator circuit and the second node directly coupled to the second input of the second comparator circuit; 
 a detection circuit coupled between a first voltage source node and the voltage divider circuit, the detection circuit generating a control signal based on the reference voltage and in response to the first power supply having a higher voltage potential than ground, the control signal controlling the turning on and off of the first and second comparator circuits; and 
 logic circuitry coupled to outputs of the first and second comparator circuits, the logic circuitry outputting a power identification signal based on signals received from the outputs of the first and second comparator circuits and the control signal generated by and received from the detection circuit, 
 wherein the detector circuit includes:
 a first MOS transistor having a source coupled to the first voltage source node; 
 a second MOS transistor having a source and a drain, the drain of the second MOS transistor coupled to a drain of the first MOS transistor; 
 a third MOS transistor having a drain coupled to a first resistor of the voltage divider, a source coupled to the first voltage source node, and a gate coupled to the drains of the first and second MOS transistors at a third node; and 
 a capacitor coupled between the first voltage source node and the third node. 
 
 
     
     
       11. The POD circuit of  claim 10 , wherein the first comparator circuit includes a differential amplifier for generating an output signal identifying if a voltage potential of the first node is at a higher potential than the reference voltage potential. 
     
     
       12. The POD circuit of  claim 11 , wherein the first comparator circuit includes fourth and fifth MOS transistors each having a gate receiving the control signal. 
     
     
       13. The POD circuit of  claim 10 , wherein the second comparator circuit includes a differential amplifier for generating an output signal identifying if a voltage potential of the second node is greater than the reference voltage potential. 
     
     
       14. The POD circuit of  claim 13 , wherein the second comparator circuit includes fourth and fifth MOS transistors each having a gate receiving the control signal. 
     
     
       15. The POD circuit of  claim 14 , wherein each of the fourth and fifth MOS transistors has a decoupling capacitor coupled across a source and a drain. 
     
     
       16. The POD circuit of  claim 10 , wherein the logic circuitry includes an AND gate receiving the control signal directly from the detection circuit as an input and outputting the power on identification signal. 
     
     
       17. The POD circuit of  claim 10 , wherein the voltage divider circuit includes first, second, and third resistors, the first and second resistors coupled together at the first node, and the second and third resistors coupled together at the second node. 
     
     
       18. The POD circuit of  claim 10 , wherein the detection circuit includes an inverter coupled between the third node and the first and second comparator circuits.