Time difference amplifier circuit

Abstract

According to one embodiment, a time difference amplifier circuit includes the first amplifier including first positive and negative inputs and first positive and negative outputs, the second amplifier including second positive and negative inputs and second positive and negative outputs, first to fourth wirings, a selection circuit including the first selection element connecting the first or fourth wirings to the second positive input, and the second selection element connecting the second or third wirings to the second negative input, and a control circuit connecting the amplifiers by the first and second wirings or by the third and fourth wirings.

What is claimed is: 
     
       1. A time difference amplifier circuit in which a plurality of time difference amplifiers are cascaded, each of the plurality of time difference amplifiers amplifying a rising edge time difference between two input signals and outputting the amplified rising edge time difference as a rising edge time difference between two output signals, and each of the plurality of time difference amplifiers including a first time difference amplifier and a second time difference amplifier, comprising:
 the first time difference amplifier configured to include a first positive input terminal, a first negative input terminal, a first positive output terminal, and a first negative output terminal; 
 the second time difference amplifier configured to include a second positive input terminal, a second negative input terminal, a second positive output terminal, and a second negative output terminal, and receive an output signal from the first time difference amplifier; 
 a first wiring configured to connect the first positive output terminal and the second positive input terminal; 
 a second wiring configured to connect the first negative output terminal and the second negative input terminal; 
 a third wiring configured to connect the first positive output terminal and the second negative input terminal; 
 a fourth wiring configured to connect the first negative output terminal and the second positive input terminal; 
 a selection circuit configured to include a first selection element and a second selection element, the first selection element connecting one of the first wiring and the fourth wiring to the second positive input terminal, and the second selection element connecting one of the second wiring and the third wiring to the second negative input terminal; 
 a control circuit configured to control the selection circuit to connect the first time difference amplifier and the second time difference amplifier by the first wiring and the second wiring, or by the third wiring and the fourth wiring so as to reduce a total time difference offset of the plurality of time difference amplifiers based on test results of characteristics of time difference offsets of the plurality of time difference amplifiers, and 
 a storage circuit configured to store information about the test results of the characteristics of the time difference offsets of the plurality of time difference amplifiers, and supply a signal based on the information to the control circuit. 
 
     
     
       2. The circuit according to  claim 1 , wherein each of the first selection element and the second selection element is formed from a selector. 
     
     
       3. The circuit according to  claim 1 , further comprising a plurality of selection circuits configured to include the selection circuit, the plurality of selection circuits being interposed between the plurality of time difference amplifiers, respectively. 
     
     
       4. The circuit according to  claim 1 , further comprising a plurality of selection circuits configured to include the selection circuit,
 wherein a first arrangement in which a selection circuit among the plurality of selection circuits is arranged, and a second arrangement in which a selection circuit among the plurality of selection circuits is not arranged exist between the plurality of time difference amplifiers. 
 
     
     
       5. The circuit according to  claim 4 , wherein the first arrangement and the second arrangement alternately exist between the plurality of time difference amplifiers.