Digitally displaying inspection system for ESD protection chip

Abstract

The present invention provides a digitally displaying inspection system for ESD protection chip, which includes an LVDS connector, a display system, first, second, and the third data lines, a power supply, and a resistor. The first, second, and third data lines each have an end electrically connected to the LVDS connector and an opposite end electrically connected to the display system. The display system includes a logic operation module and a digital display module electrically connected to the logic operation module. The logic operation module is electrically connected to the first, second, and third data lines. When an ESD protection chip is electrically connected to the LVDS connector, the logic operation module samples signals on the first, second, and third data lines and drive, after carrying out logic operations, the digital display module to display character signs, which can identify if the ESD protection chip is incorrectly connected.

What is claimed is: 
     
       1. A digitally displaying inspection system for ESD protection chip, comprising an LVDS connector, a display system, first, second, and third data lines, a power supply, and a resistor, the first, second, and third data lines each having an end electrically connected to the LVDS connector and an opposite end electrically connected to the display system, the resistor having an end electrically connected to the display system and an opposite end electrically connected to an end of the power supply, the power supply having an opposite end electrically connected to the LVDS connector, the display system comprising a logic operation module and a digital display module electrically connected to the logic operation module, the logic operation module being electrically connected to the first, second, and third data lines, whereby when an ESD protection chip is electrically connected to the LVDS connector, the logic operation module samples signals of the first, second, and third data lines and drives, after carrying out logic operation, the digital display module to display character signs. 
     
     
       2. The digitally displaying inspection system for ESD protection chip as claimed in  claim 1 , wherein the display system comprises first to fourth pins, the first data line having an end electrically connected to the first pin of the display system, the second data line having an end electrically connected to the second pin of the display system, the third data line having an end electrically connected to the third pin of the display system, the resistor having an end electrically connected to the fourth pin of the display system. 
     
     
       3. The digitally displaying inspection system for ESD protection chip as claimed in  claim 2 , wherein the LVDS connector comprises a fifth pin, a fifth opposite pin, a sixth pin, and a grounding pin, the first data line having an opposite end electrically connected to the fifth pin, the second data line having an opposite end electrically connected to the fifth opposite pin, the third data line having an opposite end electrically connected to the sixth pin. 
     
     
       4. The digitally displaying inspection system for ESD protection chip as claimed in  claim 3 , wherein the power supply has a positive terminal and a negative terminal, the resistor having an opposite end electrically connected to the positive terminal of the power supply, the negative terminal of the power supply being connected to the grounding pin of the LVDS connector so that the power supply, the resistor, the display system, the ESD protection chip, and the LVDS connector collectively form a loop. 
     
     
       5. The digitally displaying inspection system for ESD protection chip as claimed in  claim 1 , wherein the digital display module comprises a seven-segment common-anode digital display, the digital display module comprising seventh to thirteenth pins, the logic operation module applying digital signals A-G to the seventh to thirteenth pins respectively, the digital display module displaying different characters according to the digital signals A-G. 
     
     
       6. The digitally displaying inspection system for ESD protection chip as claimed in  claim 5 , wherein the seven-segment common-anode digital display comprises seven display segments a-g, the digital signals A-G respectively corresponding to the seven display segments a-g. 
     
     
       7. The digitally displaying inspection system for ESD protection chip as claimed in  claim 5 , wherein character signs displayable on the digital display module include 1, 2, 3, and 5, whereby when the first data line is individually closed, the digital display module display character sign 1; when the second data line is individually closed, the digital display module displays character sign 2; when the third data line is individually closed, the digital display module displays character sign; and when multiple data lines are closed simultaneously, the digital display module displays character sign 5. 
     
     
       8. The digitally displaying inspection system for ESD protection chip as claimed in  claim 5 , wherein the logic operation module comprises a plurality of digital logic operation units of NOT gates, OR gates, and AND gates, the logic operation module using signals of the first to third data lines to generate digital signals A-G. 
     
     
       9. The digitally displaying inspection system for ESD protection chip as claimed in  claim 8 , wherein the digital signal that the logic operation module samples on the first data line is marked X, the digital signal that the logic operation module samples on the second data line is marked Y, and the digital signal that the logic operation module samples on the third data line is marked Z, the digital signals A-G generated by the logic operation module satisfying the following relationships:
     A=  Y+Z ,    
     B=  {overscore (X)}{overscore (Y)}Z+{overscore (X)}Y{overscore (Z)}+X{overscore (Y)}{overscore (Z)} ,    
     C=  X+Z ,    
     D=  Y+Z ,    
     E=  {overscore (X)}Y{overscore (Z)} ,    
     F=  XY+XZ+YZ ,    
     G=  Y+Z .    
 
     
     
       10. The digitally displaying inspection system for ESD protection chip as claimed in  claim 9 , wherein digital signal  X  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal X, digital signal  Y  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal Y, and digital signal  Z  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal Z. 
     
     
       11. A digitally displaying inspection system for ESD protection chip, comprising an LVDS connector, a display system, first, second, and third data lines, a power supply, and a resistor, the first, second, and third data lines each having an end electrically connected to the LVDS connector and an opposite end electrically connected to the display system, the resistor having an end electrically connected to the display system and an opposite end electrically connected to an end of the power supply, the power supply having an opposite end electrically connected to the LVDS connector, the display system comprising a logic operation module and a digital display module electrically connected to the logic operation module, the logic operation module being electrically connected to the first, second, and third data lines, whereby when an ESD protection chip is electrically connected to the LVDS connector, the logic operation module samples signals of the first, second, and third data lines and drives, after carrying out logic operation, the digital display module to display character signs;
 wherein the display system comprises first to fourth pins, the first data line having an end electrically connected to the first pin of the display system, the second data line having an end electrically connected to the second pin of the display system, the third data line having an end electrically connected to the third pin of the display system, the resistor having an end electrically connected to the fourth pin of the display system; 
 wherein the LVDS connector comprises a fifth pin, a fifth opposite pin, a sixth pin, and a grounding pin, the first data line having an opposite end electrically connected to the fifth pin, the second data line having an opposite end electrically connected to the fifth opposite pin, the third data line having an opposite end electrically connected to the sixth pin; 
 wherein the power supply has a positive terminal and a negative terminal, the resistor having an opposite end electrically connected to the positive terminal of the power supply, the negative terminal of the power supply being connected to the grounding pin of the LVDS connector so that the power supply, the resistor, the display system, the ESD protection chip, and the LVDS connector collectively form a loop; 
 wherein the digital display module comprises a seven-segment common-anode digital display, the digital display module comprising seventh to thirteenth pins, the logic operation module applying digital signals A-G to the seventh to thirteenth pins respectively, the digital display module displaying different characters according to the digital signals A-G; 
 wherein the seven-segment common-anode digital display comprises seven display segments a-g, the digital signals A-G respectively corresponding to the seven display segments a-g; 
 wherein character signs displayable on the digital display module include 1, 2, 3, and 5, whereby when the first data line is individually closed, the digital display module display character sign 1; when the second data line is individually closed, the digital display module displays character sign 2; when the third data line is individually closed, the digital display module displays character sign; and when multiple data lines are closed simultaneously, the digital display module displays character sign 5; 
 wherein the logic operation module comprises a plurality of digital logic operation units of NOT gates, OR gates, and AND gates, the logic operation module using signals of the first to third data lines to generate digital signals A-G; 
 wherein the digital signal that the logic operation module samples on the first data line is marked X, the digital signal that the logic operation module samples on the second data line is marked Y, and the digital signal that the logic operation module samples on the third data line is marked Z, the digital signals A-G generated by the logic operation module satisfying the following relationships:
     A=  Y+Z ,    
     B=  {overscore (X)}{overscore (Y)}Z+{overscore (X)}Y{overscore (Z)}+X{overscore (Y)}{overscore (Z)} ,    
     C=  X+Z ,    
     D=  Y+Z ,    
     E=  {overscore (X)}Y{overscore (Z)} ,    
     F=  XY+XZ+YZ ,    
     G=  Y+Z   ; and 
 
 wherein digital signal  X  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal X, digital signal  Y  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal Y, and digital signal  Z  is obtained by a NOT gate of the logic operation module carrying out an operation on the digital signal Z.