Flat panel display device and method of manufacturing the same

Abstract

A method of manufacturing a flat panel display device includes: forming a semiconductor layer of a thin film transistor (TFT) on a substrate; forming a gate electrode on the semiconductor layer with a gate insulating layer between the gate electrode and the semiconductor layer, and doping source and drain regions of the semiconductor layer with ion impurities; sequentially forming a first conductive layer, a first insulating layer, and a second conductive layer, and forming a capacitor at a distance away from the TFT by patterning the first conductive layer, the first insulating layer, and the second conductive layer; forming a second insulating layer, and forming contact holes passing through the second insulating layer, the contact holes exposing portions of the source and drain regions and the second conductive layer; and forming source and drain electrodes that respectively contact the source and drain regions and the second conductive layer through the contact holes.

What is claimed is: 
     
       1. A flat panel display device comprising:
 a semiconductor layer of a thin film transistor (TFT) on a substrate, the semiconductor layer comprising a channel region, a source region, and a drain region; 
 a gate electrode on the channel region with a gate insulating layer between the gate electrode and the channel region; 
 a capacitor on the gate insulating layer and comprising a first conductive layer, a first insulating layer, and a second conductive layer of which etched side surfaces are aligned; 
 source and drain electrodes passing through a second insulating layer on the gate electrode and the capacitor, the source electrode contacting the source region and the drain electrode contacting drain region, one of the source electrode and drain electrode contacting the second conductive layer; and 
 a pixel electrode contacting a portion of one of the source and drain electrodes. 
 
     
     
       2. The flat panel display device of  claim 1 , wherein the source and drain regions comprise same ion impurities. 
     
     
       3. The flat panel display device of  claim 1 , further comprising a wiring formed of a same material as that of the gate electrode, the wiring being on the gate insulating layer on which the gate electrode is formed and directly contacting the first conductive layer. 
     
     
       4. The flat panel display device of  claim 3 , wherein the wiring comprises at least one conductive material selected from the group consisting of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), molybdenum tungsten (MoW), aluminum/copper (Al/Cu), and combinations thereof. 
     
     
       5. The flat panel display device of  claim 1 , wherein each of the first conductive layer and the second conductive layer of the capacitor comprises a transparent conductive material. 
     
     
       6. The flat panel display device of  claim 5 , wherein the transparent conductive material comprises at least one material selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). 
     
     
       7. The flat panel display device of  claim 1 , wherein the first insulating layer comprises a material having a dielectric constant higher than that of the second insulating layer. 
     
     
       8. The flat panel display device of  claim 1 , wherein the first insulating layer comprises a nitride. 
     
     
       9. The flat panel display device of  claim 1 , wherein the first insulating layer is only between the first conductive layer and the second conductive layer. 
     
     
       10. The flat panel display device of  claim 1 , further comprising an organic layer between the source and drain electrodes and the pixel electrode,
 wherein one of the source and drain electrodes contacts the pixel electrode through a via-hole in the organic layer. 
 
     
     
       11. The flat panel display device of  claim 1 , further comprising:
 a counter electrode facing the pixel electrode; and 
 a liquid crystal layer between the pixel electrode and the counter electrode. 
 
     
     
       12. The flat panel display device of  claim 1 , further comprising a wiring formed of a same material as that of the gate electrode, the wiring being on the gate insulating layer on which the gate electrode is formed and directly contacting the first conductive layer,
 wherein the wiring is for receiving a voltage Vcom. 
 
     
     
       13. The flat panel display device of  claim 1 , further comprising:
 a counter electrode facing the pixel electrode; and 
 an organic light-emitting layer between the pixel electrode and the counter electrode.