Programmable memory with skewed replica and redundant bits for reset control

Abstract

Embodiments of a circuit and method for setting initial trim bits in an integrated circuit (IC) are described. The circuit includes a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of the IC following energizing of the IC. The memory array further includes replica bit circuitry to generate a number of replica bits. A logic circuit coupled to the memory array and the main circuit of the IC is configured to receive the replica bits, and to provide a signal to the IC that indicates when the trim bits are valid. In one embodiment, the circuit further includes redundancy check logic configured to receive a number of the trim bits from the memory array, compare the number of trim bits to a pre-determined or computed value, and to provide a BITS_OK signal to the logic circuit.

What is claimed is: 
     
       1. An initial trim circuit comprising:
 a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of an integrated circuit (IC) including the initial trim circuit following energizing of the IC, the memory array comprising replica bit circuitry to generate a number of replica bits, wherein the replica bit circuitry is configured to generate the number of replica bits using a current through the replica bit circuitry skewed relative to a current through the plurality of trim bit cells; and 
 a logic circuit coupled to the memory array and the IC, the logic circuit configured to receive the number of replica bits and to provide a signal to the main circuit of the IC that indicates when the trim bits are valid. 
 
     
     
       2. The circuit of  claim 1 , wherein the number of replica bits include at least a replica zero bit and a replica one bit. 
     
     
       3. The circuit of  claim 1 , wherein the replica bit circuitry comprises a circuit similar to that of the plurality of trim bit cells. 
     
     
       4. The circuit of  claim 1 , wherein the current through the replica bit circuitry is skewed by 10% relative to the current through the plurality of trim bit cells. 
     
     
       5. The circuit of  claim 1 , wherein the replica bit circuitry is configured so that the number of replica bits resolve at a higher supply voltage than the trim bits. 
     
     
       6. The circuit of  claim 1 , wherein the logic circuit is further configured so that the signal to the IC also turns off the memory array. 
     
     
       7. The circuit of  claim 1 , further comprising redundancy check logic configured to receive a number of trim bits from the memory array, compare the number of trim bits received from the memory array to a predetermined value and to provide a BITS_OK signal to the logic circuit. 
     
     
       8. An initial trim circuit comprising:
 a memory array including a plurality of trim bit cells to store and provide trim bits to trim registers in a main circuit of an integrated circuit (IC) including the initial trim circuit following energizing of the IC, the memory array further comprising replica bit circuitry to generate a number of replica bits, wherein the replica bit circuitry is configured to generate the number of replica bits using a current through the replica bit circuitry skewed relative to a current through the plurality of trim bit cells; 
 redundancy check logic configured to receive a number of trim bits from the memory array, compare the number of trim bits to a predetermined value and generate a BITS_OK signal; and 
 a logic circuit coupled to the memory array, redundancy check logic and the IC, the logic circuit configured to receive the number of replica bits, the BITS_OK signal, and to provide a signal to the main circuit of the IC that indicates when the trim bits are valid. 
 
     
     
       9. The circuit of  claim 8 , wherein the number of replica bits include at least a replica zero bit and a replica one bit. 
     
     
       10. The circuit of  claim 8 , wherein the replica bit circuitry comprises a circuit similar to that of the plurality of trim bit cells. 
     
     
       11. The circuit of  claim 8 , wherein the current through the replica bit circuitry is skewed by 10% relative to the current through the plurality of trim bit cells. 
     
     
       12. The circuit of  claim 8 , wherein the replica bit circuitry is configured so that the number of replica bits resolve at a higher supply voltage than the trim bits. 
     
     
       13. The circuit of  claim 8 , wherein the logic circuit is further configured so that the signal to the IC also turns off the memory array. 
     
     
       14. A method comprising:
 storing trim bits for an integrated circuit (IC) in a memory array; 
 coupling the trim bits to trim registers in a main circuit of the IC following energizing of the IC; 
 generating a number of replica bits with replica bit circuitry in the memory array, wherein generating the number of replica bits comprises a current through the replica bit circuitry skewed relative to a current through trim bit cells in the memory array; 
 receiving the number of replica bits in a logic circuit coupled to the memory array and the IC; and 
 providing a signal to the main circuit of the IC that indicates when the trim bits are valid and to begin a boot process. 
 
     
     
       15. The method of  claim 14 , wherein the replica bit circuitry is configured so that generating the number of replica bits comprises providing the replica bit circuitry a higher supply voltage than that needed to resolve the trim bits provided to the main circuit of the IC. 
     
     
       16. The method of  claim 14 , wherein providing the signal to the main circuit of the IC further comprises providing a signal to the memory array to turn off the memory array. 
     
     
       17. The method of  claim 14 , further comprising:
 receiving in redundancy check logic a number of trim bits; 
 comparing the number of trim bits to a predetermined value; and 
 providing a BITS_OK signal to the logic circuit.