US8846503B1ActiveUtility

Self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane

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Assignee: NAT UNIV TSING HUAPriority: Aug 2, 2013Filed: Aug 26, 2013Granted: Sep 30, 2014
Est. expiryAug 2, 2033(~7.1 yrs left)· nominal 20-yr term from priority
H10P 14/3214H10P 14/2905H10P 14/274H10P 14/271H10W 10/181H10P 90/1906H10D 84/08H01L 21/02645H01L 21/02455H01L 21/02532H01L 21/02381H01L 21/02639H01L 21/02647
68
PatentIndex Score
2
Cited by
8
References
9
Claims

Abstract

The present invention relates to a self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane. By using this method, two semiconductor materials heterogeneous to each other can be laterally assembled in a self-alignment way, without using any epitaxial buffer layers or gradient buffer layers. Therefore, when applying this method to fabricating an electronic device having heterojunction, not only the manufacture cost can be effectively reduced, but the difficulty of manufacturing process can also be overcome. Moreover, in this method, one amorphous heterogeneous semiconductor material would laterally grow to a crystal semiconductor material through epitaxy after being treated the rapid melting growth (RMG) process, and the epitaxial crystal semiconductor material would then be laterally assembled with the other one semiconductor material on an identical substrate, for carrying out the lateral assembly of the two heterogeneous semiconductor materials by using the self-alignment way and the smallest thermal budget.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane, comprising the steps of:
 (1) fabricating a substrate; 
 (2) forming a first semiconductor material and a first oxide layer on the substrate; 
 (3) treating lithography etching process to the first semiconductor material and the first oxide layer, so as to make the first semiconductor material to a stepped semiconductor layer on the substrate, wherein the stepped semiconductor layer comprises a bottom layer and a stair layer, and a height difference is formed between the bottom layer and the stair layer; 
 (4) forming an isolation layer for covering the substrate, the stepped semiconductor layer and the first oxide layer except for a plurality of through holes opened on the bottom layer of the stepped semiconductor layer, wherein the through holes are used as epitaxy seed windows; 
 (5) forming a second semiconductor material on the isolation layer, wherein part of the second semiconductor material would be filled into the through holes, so as to contact with the bottom layer of the stepped semiconductor layer; 
 (6) treating lithography and etching process to define the second semiconductor material, so as to make the second semiconductor material to be a bar-shaped semiconductor covering the through holes and being across the step of the first semiconductor to form a disconnected overlapped semiconductor, wherein the bar-shaped semiconductor and the overlapped semiconductor are formed on the bottom layer and the stair layer of the stepped semiconductor layer, respectively; 
 (7) forming a second oxide layer for covering the product of the aforesaid step (6), and modulating the thickness of the second oxide layer to completely cover the stepped semiconductor layer; 
 (8) treating a rapid thermal anneal process to the product of the aforesaid step (7), so as to make the bar-shaped semiconductor laterally grow from the seed windows on the bottom layer toward the stair layer of the stepped semiconductor layer through epitaxy; 
 (9) treating a wet etching process to the product of the aforesaid step (8), so as to remove the first oxide layer, the isolation layer, and the overlapped semiconductor on the stair layer, and the second oxide layer; and 
 (10) a crystallized bar-shaped semiconductor layer is formed on the bottom layer of the stepped first semiconductor, wherein one end surface of the crystallized bar-shaped semiconductor layer is terminated to the vertical end surface of the stair layer of the stepped semiconductor layer. 
 
     
     
       2. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 1 , further comprising the steps of:
 (11) forming a passivation layer on the substrate, the stepped semiconductor layer and the crystallized bar-shaped semiconductor layer. 
 
     
     
       3. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 1 , wherein the substrate is selected from the group consisting of: silicon substrate, SOI (silicon on insulator) substrate and sapphire substrate. 
     
     
       4. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 1 , wherein the first semiconductor material is silicon (Si) and the material of the isolation layer is oxide (SiO 2 ). 
     
     
       5. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 4 , wherein the second semiconductor material is a heterogeneous material opposite to the first semiconductor material. 
     
     
       6. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 5 , wherein the heterogeneous material is selected from the group consisting of: germanium (Ge), silicon germanium (Si 1-x Ge x ), II-VI compound semiconductor material, and III-V compound semiconductor material. 
     
     
       7. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 6 , wherein the aforesaid III-V compound semiconductor material is selected from the group consisting of: gallium arsenide (GaAs), indium phosphide (InP), aluminum gallium arsenide (Al x Ga 1-x As), indium gallium phosphide (InGaP), and indium gallium arsenide phosphide (InGaAsP). 
     
     
       8. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 4 , wherein the second semiconductor material is a homogeneous material opposite to the first semiconductor material. 
     
     
       9. The self-aligned and lateral-assembly method for integrating heterogeneous material structures on the same plane of  claim 8 , wherein the homogeneous material is selected from the group consisting of: silicon (Si), silicon carbide (SiC) and silicon nitride (Si 3 N 4 ).

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