Through silicon via packaging structures and fabrication method

Abstract

A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.

What is claimed is: 
     
       1. A method for fabricating a through silicon via packaging structure, comprising:
 providing a first type substrate, 
 epitaxially growing a second type substrate directly from a surface of the first type substrate, different from the first type substrate, wherein the epitaxially-grown second type substrate has a first surface and a second surface on the first type substrate; 
 forming a semiconductor device on the first surface of the epitaxially-grown second type substrate; 
 forming an interlayer dielectric layer on the first surface of the epitaxially-grown second type substrate and a surface of the semiconductor device; 
 forming a metal interconnection structure in the interlayer dielectric layer electrically connecting with the semiconductor device; 
 forming a through silicon via structure perforating an entire thickness of the epitaxially-grown second type substrate and perforating an entire thickness of the interlayer dielectric layer, the through silicon via structure electrically connecting with the metal interconnection structure by a metal layer on a top surface of the dielectric layer; and 
 after forming the through silicon via structure, removing the first type substrate to expose the second surface of the epitaxially-grown second type substrate and a bottom surface of the through silicon via structure. 
 
     
     
       2. The method according to  claim 1 , wherein:
 the first type substrate is a silicon germanium substrate; and 
 the second type substrate is a silicon substrate. 
 
     
     
       3. The method according to  claim 2 , wherein removing the first type substrate further includes:
 removing the silicon germanium substrate using a gas etching process or a wet etching process. 
 
     
     
       4. The method according to  claim 2 , wherein:
 thickness of the silicon germanium substrate is in a range approximately 50 μm-750 μm. 
 
     
     
       5. The method according to  claim 2 , further comprising:
 controlling a thickness of the silicon substrate in a range approximately 10 μm-100 μm by the epitaxially growing of the silicon substrate as the second type substrate. 
 
     
     
       6. The method according to  claim 2 , before removing the first type substrate, further including:
 performing a back-grinding process to thin the silicon germanium substrate as the first type substrate to a certain thickness. 
 
     
     
       7. The method according to  claim 3 , wherein:
 etching liquid of the wet etching process is a hot HCl solution. 
 
     
     
       8. The method according to  claim 3 , wherein:
 etching gas of the gas etching process is HCl; 
 gas flow is in range of approximately 20 sccm-200 sccm; 
 pressure of a reaction chamber is in a range of approximately 0.05 Torr-1 Torr; and 
 temperature of the reaction chamber is in a range of approximately 300° C. 
 
     
     
       9. The method according to  claim 3 , wherein:
 selectivity ratio of the wet etching process or the gas etching process is greater than 100:1 to the silicon germanium substrate and the silicon substrate to reduce damage to the silicon substrate when removing the silicon germanium substrate. 
 
     
     
       10. The method according to  claim 1 , before removing the silicon germanium substrate, further including:
 forming a bonding layer on the interlayer dielectric layer; and 
 bonding a carrier substrate with the interlayer dielectric layer using the bonding layer. 
 
     
     
       11. The method according to  claim 10 , after removing the silicon germanium substrate, further including:
 forming a bottom interconnection layer on the second surface of the silicon substrate and the bottom surface of the through silicon via structure; 
 forming a second passivation layer on the bottom interconnection layer and the second surface of the silicon substrate; 
 patterning the second passivation layer to expose a portion of the bottom interconnection layer; and 
 forming a second solder dot on the bottom interconnection layer. 
 
     
     
       12. The method according to  claim 11 , after forming the second solder dot, further including:
 peeling off the carrier substrate from the interlayer dielectric layer by a high temperature baking process or a soaking process. 
 
     
     
       13. The method according to  claim 12 , wherein:
 temperature of the high temperature baking process is in range of approximately 120 ° C.-200 ° C. 
 
     
     
       14. The method according to  claim 1 , after forming the through silicon via structure, further including:
 forming a first passivation layer on the interlayer dielectric layer; and 
 forming a first solder dot to electrically connect with the metal interconnection structure. 
 
     
     
       15. The method according to  claim 2 , wherein:
 molar percentage germanium of the silicon germanium substrate is in a range of approximately 40%-90% to provide an etching selectivity ratio greater than 100:1 to the silicon germanium substrate and the silicon substrate.