Thin film transistor substrate and method of fabricating the same

Abstract

Disclosed are a thin film transistor substrate and a method of fabricating the same in which the number of processes is reduced. The method includes forming a first conductive pattern including gate electrodes and gate lines on a substrate through a first mask process, depositing a gate insulating film and forming a second conductive pattern including a semiconductor pattern, source and drain electrodes and data lines through a second mask process, depositing first and second passivation films and forming pixel contact holes passing through the first and second passivation films and exposing the drain electrodes through a third mask process, and forming a third conductive pattern including a common electrode and a common line and forming a third passivation film formed in an undercut structure with the common electrode through a fourth mask process, simultaneously, and forming a fourth conductive pattern including pixel electrodes through a lift-off process.

What is claimed is: 
     
       1. A thin film transistor substrate, comprising:
 a gate line; 
 a data line intersecting the gate line; 
 a thin film transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode formed opposite the source electrode, and a semiconductor pattern overlapping the gate electrode such that a gate insulating film is interposed between the semiconductor pattern and the gate electrode; 
 first and second passivation films covering the thin film transistor; 
 a common electrode formed on the second passivation film; 
 a third passivation film formed on the common electrode; 
 a plurality of grooves formed on a top of the third passivation film and 
 a pixel electrode formed within the plurality of grooves; 
 wherein first to third passivation films includes a pixel contact hole to expose the drain electrode of the thin film transistor, such that the pixel electrode is connected to the drain electrode via the pixel contact hole, 
 wherein the common electrode is separated from the pixel electrode by a space provided by an undercut structure with the third passivation film, and 
 wherein the common electrode and the pixel electrode form a fringe field. 
 
     
     
       2. The thin film transistor substrate according to  claim 1 , further comprising:
 gate pad connected to the gate line; and 
 data pad connected to the data line. 
 
     
     
       3. The thin film transistor substrate according to  claim 2 , wherein the gate pad includes:
 a gate pad lower electrode connected to the gate line; 
 first to fourth gate contact holes passing through the first to third passivation films and the gate insulating film; and 
 a gate pad upper electrode connected to the gate pad lower electrode, formed of a same material as the pixel electrode in a same layer as the pixel electrode, and separated from the common electrode by the space provided by the undercut structure. 
 
     
     
       4. The thin film transistor substrate according to  claim 2 , wherein the data pad includes:
 a data pad lower electrode connected to the data line; 
 first to third data contact holes passing through the first to third passivation films; and 
 a data pad upper electrode connected to the data pad lower electrode, formed of a same material as the pixel electrode in a same layer as the pixel electrode, and separated from the common electrode by the space provided by the undercut structure. 
 
     
     
       5. The thin film transistor substrate according to  claim 1 , wherein a thickness of the pixel electrode is greater than a thickness of the common electrode. 
     
     
       6. The thin film transistor substrate according to  claim 1 , wherein a width of the third passivation film is smaller than a width of the second passivation film.