Techniques for developing a negative impedance

Abstract

Techniques to develop negative impedance circuits that may operate to their power supply rails. The techniques may include generating currents in response to voltage signals presented at respective input terminals of a negative impedance circuit. The voltage signals may be differential signals. The generated currents may be driven through a common impedance within the negative impedance circuit. The currents flowing through the common impedance may be mirrored back to the input terminals of the negative impedance circuit. The negative impedance circuit may be controlled to operate about a common-mode voltage for the circuit.

I claim: 
     
       1. A circuit system, comprising:
 a first resistance; 
 a negative impedance circuit operatively connected to the first resistance and having current generators each generating currents in response to a voltage presented at respective input terminals of the negative impedance circuit;
 a second resistance coupled to both current generators; and 
 a pair of current mirrors each to mirror currents from a respective current generator to one of the input terminals. 
 
 
     
     
       2. The circuit system of  claim 1 , wherein the value of the first resistance is equal to the value of the second resistance. 
     
     
       3. The circuit system of  claim 1 , wherein the value of the first resistance is less than the value of the second resistance. 
     
     
       4. The circuit system of  claim 1 , wherein the first resistance is operatively connected in parallel with the negative impedance circuit. 
     
     
       5. The circuit system of  claim 1 , wherein the first resistance is operatively connected in series with the negative impedance circuit. 
     
     
       6. The circuit system of  claim 1 , wherein the current generators are a pair of op-amps. 
     
     
       7. The circuit system of  claim 6 , wherein the current mirrors are integrated into respective output stages for each op-amp. 
     
     
       8. The circuit system of  claim 1 , wherein the current generators are a differential op-amp. 
     
     
       9. The circuit system of  claim 8 , wherein the current mirrors are integrated into respective output stages for the differential op-amp. 
     
     
       10. A circuit system, comprising:
 a first resistance; 
 a negative impedance operatively connected to the first resistance and having current generators each generating a predetermined current;
 a pair of level shifting transistors each receiving a current from a respective current generator and driving the current through a second resistance; and 
 a pair of current mirrors each to mirror currents from a respective level shifting transistor to respective input terminals of the negative impedance circuit. 
 
 
     
     
       11. The circuit system of  claim 10 , wherein the value of the first resistance is equal to the value of the second resistance. 
     
     
       12. The circuit system of  claim 10 , wherein the value of the first resistance is less than the value of the second resistance. 
     
     
       13. The circuit system of  claim 10 , wherein the first resistance is operatively connected in parallel with the negative impedance circuit. 
     
     
       14. The circuit system of  claim 10 , wherein the first resistance is operatively connected in series with the negative impedance circuit. 
     
     
       15. A negative impedance circuit, comprising:
 a pair of op-amps for generating a current through a common impedance in response to each receiving one of a pair of differential input voltages; and 
 a pair of current mirrors for mirroring the current from each op-amp to input terminals at which the differential input voltages are received. 
 
     
     
       16. The circuit of  claim 15 , wherein the value of the common impedance determines a negative impedance value for the circuit. 
     
     
       17. The circuit of  claim 15 , wherein each of the op-amps are configured in a positive feedback manner. 
     
     
       18. The circuit of  claim 15 , further comprising:
 a common-mode voltage controller having a pair of differential outputs coupled to the respective input terminals. 
 
     
     
       19. The circuit of  claim 15 , wherein the pair of current mirrors are integrated into respective output stages for each op-amp. 
     
     
       20. A negative impedance circuit, comprising:
 a differential op-amp for generating a current through a common impedance in response to receiving a pair of differential input voltages; and 
 a pair of current mirrors for mirroring the current from each of the respective outputs to input terminals at which the differential input voltages are received. 
 
     
     
       21. The circuit of  claim 20 , wherein the value of the common impedance determines a negative impedance value for the circuit. 
     
     
       22. The circuit of  claim 20 , wherein the pair of current mirrors are integrated into respective output stages for the differential op-amp. 
     
     
       23. A negative impedance circuit, comprising:
 a pair of current sources; 
 a pair of level shifting transistors each connected at its drain to a respective current source, connected at its gate to one of a pair of differential input terminals, and connected at its source to a common impedance; 
 a pair of op-amps each connected at an input to a respective level shifting transistor drain and having an output connected to another of its inputs; and 
 a pair of current mirrors each having a current input connected to a respective level shifting transistor source, a current output connected to one of the pair of differential input terminals, and a current control coupled to an output of a respective op-amp. 
 
     
     
       24. The circuit of  claim 23 , wherein the value of the common impedance determines a negative impedance value for the circuit. 
     
     
       25. The circuit of  claim 23 , further comprising:
 a respective bootstrapping voltage coupled to each of the respective level shifting transistor gates. 
 
     
     
       26. A method for developing a negative impedance, comprising:
 generating currents in response to each of a pair of differential input voltages; 
 passing the currents through a common impedance; and 
 mirroring the currents to input terminals at which the differential voltages are received. 
 
     
     
       27. The method of  claim 26 , the generating further comprising:
 generating the currents from a pair of op-amps having outputs coupled to the common impedance. 
 
     
     
       28. The method of  claim 27 , wherein the currents are mirrored from a respective output stage of each of the pair of op-amps. 
     
     
       29. The method of  claim 27 , the generating further comprising:
 balancing, in an active manner, the differential input voltages to a predetermined common-mode voltage. 
 
     
     
       30. The method of  claim 29 , wherein the balancing is managed by a common-mode voltage controller. 
     
     
       31. The method of  claim 26 , the generating further comprising:
 generating the currents from a pair of transistors each having a gate coupled to one of the differential input voltages and a source coupled in an opposing configuration to the common impedance. 
 
     
     
       32. The method of  claim 31 , wherein the currents are mirrored from a respective transistor current mirror of each source follow transistor. 
     
     
       33. The method of  claim 26 , the generating further comprising:
 generating the currents from a differential op-amp having differential outputs coupled in an opposing configuration to the common impedance.