Configurable digital-analog phase locked loop

Abstract

A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.

What is claimed is: 
     
       1. A phase locked loop (PLL) device comprising:
 a phase detector; 
 an analog loop filter comprising a plurality of filter elements; 
 a voltage controlled oscillator (VCO); 
 a time to digital converter (TDC); 
 a digital loop filter; 
 a digital to analog converter (DAC); and 
 a switching mechanism responsive to a first control signal value to configure the PLL device into an analog loop comprising the phase detector, analog loop filter, and VCO and responsive to a second control signal value to configure the PLL device into a hybrid digital-analog loop comprising the phase detector, TDC, DAC, and VCO and further configured to connect the plurality of filter elements to form an integrator between the DAC and the VCO. 
 
     
     
       2. The PLL device of  claim 1 , wherein the DAC comprises a current source output stage connected to the integrator when the PLL device is configured in the hybrid digital-analog loop. 
     
     
       3. The PLL device of  claim 1 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter when the PLL device is configured in the analog loop. 
     
     
       4. The PLL device of  claim 3 , wherein the switching element is configured to connect the plurality of filter elements to form the analog loop filter having a response comprising a first pole at an origin, a zero at a first frequency and a second pole a second frequency greater than the first frequency. 
     
     
       5. The PLL device of  claim 3 , further comprising a charge pump connected between the phase detector and the analog loop filter when the PLL device is configured in the analog loop. 
     
     
       6. The PLL device of  claim 5 , wherein the switching mechanism disables the charge pump when the PLL device is configured in the hybrid digital-analog loop. 
     
     
       7. The PLL device of  claim 1 , further comprising a dual point modulation port comprising a lower frequency modulation port for combining a data signal with a reference signal received by the phase detector and an upper frequency port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       8. The PLL device of  claim 1 , further comprising a dual point modulation port comprising a lower frequency modulation port for combining a data signal with a feedback signal provided by a feedback between the VCO and the phase detector and an upper frequency port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       9. The PLL device of  claim 8 , wherein the lower frequency modulation port uses sigma delta modulation. 
     
     
       10. A phase locked loop (PLL) device comprising:
 phase detector means for detecting a phase difference; 
 analog loop filter means for analog loop filtering, the analog loop filter means comprising a plurality of filter element means; 
 voltage controlled oscillator (VCO) means for generating a VCO signal; 
 time to digital converter (TDC) means for converting a time period to a digital number; 
 digital loop filter means for digital filtering; 
 digital to analog converter (DAC) means for converting a digital signal into an analog signal; and 
 switching means for configuring the PLL device in an analog loop comprising the phase detector means, analog loop filter means, and VCO means in response to a first control signal and for configuring the PLL device in a hybrid digital-analog loop comprising the phase detector means, TDC means, DAC means, and VCO means in response to a second control signal, the switching means further configured to connect the plurality of filter element means to form an integrator means for integrating a current signal generated by the DAC means, the integrator means connected between the DAC means and the VCO means when the switching means configures the PLL device in the hybrid digital-analog loop. 
 
     
     
       11. The PLL device of  claim 10 , wherein the DAC means comprises a current source output stage means connected to the integrator means when the PLL device is configured in the hybrid digital-analog loop. 
     
     
       12. The PLL device of  claim 10 , wherein the switching element means is configured to connect the plurality of filter element means to form the analog loop filter means when the PLL device is configured in the analog loop. 
     
     
       13. The PLL device of  claim 12 , wherein the switching element means is configured to connect the plurality of filter element means to form the analog loop filter means having a response comprising a first pole at an origin, a zero at a first frequency and a second pole at a second frequency greater than the first frequency when the PLL device is configured in the analog loop. 
     
     
       14. The PLL device of  claim 12 , further comprising a charge pump means for generating an analog loop signal based on an analog correction signal provided by the phase detector means, the charge pump means connected between the phase detector means and the analog loop filter means when the PLL device is configured in the analog loop. 
     
     
       15. The PLL device of  claim 14 , wherein the switching means is for disabling the charge pump when the PLL device is configured in the hybrid digital-analog loop. 
     
     
       16. The PLL device of  claim 10 , further comprising a dual point modulation means for modulating the VCO output signal, the dual point modulation means comprising a lower frequency modulation port means for combining a data signal with a reference signal received by the phase detector means and an upper frequency modulation port means for combining the data signal with a digital filter output signal provided by the digital loop filter means. 
     
     
       17. The PLL device of  claim 10 , further comprising a dual point modulation means modulating the VCO output signal, the dual point modulation means comprising a lower frequency modulation port means for combining a data signal with a feedback signal provided by a feedback means between the VCO means and the phase detector means and an upper frequency port means for combining the data signal with a digital filter output signal provided by the digital loop filter means. 
     
     
       18. The PLL device of  claim 17 , wherein the lower frequency port means uses sigma delta modulation. 
     
     
       19. A method for managing a phase locked loop, the method comprising:
 connecting, in response to first control signal value, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO) to configure the PLL device in an analog loop; and 
 connecting, in response to a second control signal value, at least the phase detector, a time to digital converter (TDC), a digital loop filter, a digital to analog converter (DAC), the VCO, and a plurality of filter elements of the analog loop filter to form an integrator between the DAC and the VCO to configure the PLL device in a hybrid digital-analog loop. 
 
     
     
       20. The method of  claim 19 , wherein the connecting to form the hybrid digital-analog loop comprises connecting a current source output stage in the DAC to the integrator. 
     
     
       21. The method of  claim 20 , wherein the connecting to form the hybrid digital-analog loop comprises disabling a charge pump. 
     
     
       22. The method of  claim 19 , wherein the connecting to form the analog loop comprises connecting the plurality of filter elements to form the analog loop filter. 
     
     
       23. The method of  claim 22 , wherein connecting the plurality of filter elements to form the analog loop filter comprises connecting the plurality of filter elements to form the analog loop filter having a response comprising a first pole at an origin, a zero at a first frequency and a second pole a second frequency greater than the first frequency. 
     
     
       24. The method device of  claim 19 , wherein the connecting to form the analog loop further comprises connecting a charge pump between the phase detector and the analog loop filter. 
     
     
       25. The method of  claim 19 , further comprising modulating a VCO output signal of the VCO through a two point modulation port comprising a lower frequency modulation port for combining a data signal with a reference signal received by the phase detector and an upper frequency modulation port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       26. The method of  claim 19 , further comprising modulating a VCO output signal of the VCO through a two point modulation port comprising a lower frequency modulation port for combining a data signal with a feedback signal received by the phase detector from the VCO through a feedback and an upper frequency modulation port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       27. The method of  claim 26 , wherein the lower frequency modulation port uses sigma delta modulation. 
     
     
       28. A computer-readable medium encoded with computer-executable instructions, the execution of the computer-executable instructions for:
 connecting, in response to first control signal value, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO) to configure the PLL device in an analog loop; and 
 connecting, in response to a second control signal value, at least the phase detector, a time to digital converter (TDC), a digital loop filter, a digital to analog converter (DAC), the VCO and a plurality of filter elements of the analog loop filter to form an integrator between the DAC and the VCO to configure the PLL device in a hybrid digital-analog loop. 
 
     
     
       29. The computer-readable medium of  claim 28 , wherein the connecting to form the hybrid digital-analog loop comprises connecting a current source output stage in the DAC to the integrator. 
     
     
       30. The computer-readable medium of  claim 29 , wherein the connecting to form the hybrid digital-analog loop comprises disabling a charge pump. 
     
     
       31. The computer-readable medium of  claim 28 , wherein the connecting to form the analog loop comprises connecting the plurality of filter elements to form the analog loop filter. 
     
     
       32. The computer-readable medium of  claim 31 , wherein connecting the plurality of filter elements to form the analog loop filter comprises connecting the plurality of filter elements to form the analog loop filter having a response comprising a first pole at an origin, a zero at a first frequency and a second pole a second frequency greater than the first frequency. 
     
     
       33. The computer-readable medium of  claim 28 , wherein the connecting to form the analog loop further comprises connecting a charge pump between the phase detector and the analog loop filter. 
     
     
       34. The computer-readable medium of  claim 28 , further comprising modulating a VCO output signal of the VCO through a two point modulation port comprising a lower frequency modulation port for combining a data signal with a reference signal received by the phase detector and an upper frequency modulation port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       35. The computer-readable medium of  claim 28 , further comprising modulating a VCO output signal of the VCO through a two point modulation port comprising a lower frequency modulation port for combining a data signal with a feedback signal received by the phase detector from the VCO through a feedback and an upper frequency modulation port for combining the data signal with a digital filter output signal provided by the digital loop filter. 
     
     
       36. The computer-readable medium of  claim 35 , wherein the lower frequency modulation port uses sigma delta modulation.